On 11/6/2022 3:17 PM, Sarthak Rout via gem5-users wrote:
Hello everyone,
I am trying to use MSR registers for experimenting on caches. I want to add a custom MSR to the
system which is simulated by Gem5 with Linux v5.4.84 kernel. I have added entries in
src/arch/x86/regs/msr.cc and src/arch/x86/regs/misc.hh on some unused register
index, say 0xc0010118.
After compiling and building gem5.opt, when I run sudo rdmsr 0xc0010118, it
says,
rdmsr: CPU 0 cannot read MSR 0xc0010118
Analysing it with strace shows that pread64 returns EIO (input/output error).
I wonder if you updated src/arch/x86/regs/misc.hh:isValidMiscReg to allow that
number to be accessed. Of course the index needs to be added to enum
MiscRegIndex, but you probably did that. I also defined a BitUnion64 to
define the fields of the reg. I also:
- Added a case to src/arch/x86/isa.cc that does nothing, and may not be needed
since the default case also seems to do nothing.
- Added code in src/arch/x86/process.cc:X86_64Process::initState to initialize
my new register, and likewise in I386Process::initState.
Of course I added functionality related to the semantics of the register, but
that's distinct from the above.
HTH - Eliot Moss
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