[gem5-users] gem5.org Maintenance

gem5.org is undergoing some maintenance. Please let us know if you have any trouble accessing services on gem5.org Monday morning. Thanks, Ali ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo

Re: [gem5-users] simulation speed (FreeBSD)

For linux we pass in a jiffies= on the command line so Linux doesn¹t attempt to calculate it on boot. Perhaps FreeBSD is doing some type of calibration like jiffies and that is taking the time? Thanks, Ali On 4/14/15, 2:35 AM, "Ruslan Bukin" wrote: >Hello, > >I experience a speed problem runni

Re: [gem5-users] InOrder ARM processor

Minor simulates an in-order processor accurately. Ali > On Nov 6, 2015, at 3:37 AM, Khaled Attia wrote: > > Hello again Fernando, > So, does minorCPU accurately simulate an InOrder ARM processor? I’ve read > your 2014 paper in SAMOS about simulation of inorder cores using out-of-order > mode

Re: [gem5-users] Cache configuration not visible from m5term for ARM full FS simulation

The caches aren’t necessarily listed in the lscpu especially on ARM platforms. Ali > On Nov 17, 2015, at 7:04 AM, rahul shrivastava > wrote: > > Hi, > > I am trying to simulate the ARM system with L1 cache. I can see in config.ini > the detailed configuratio

Re: [gem5-users] Running parsec simlarge

What model are you using to get to the ROI? Typically people get to the ROI with the atomic cpu and then simulate the ROI with the o3 CPU. Ali > On Jan 10, 2016, at 7:06 AM, Nizamudheen Ahmed wrote: > > Hi champs > > I am trying to run parsec benchmarks for 'simlarge' configuration on gem5 in

[gem5-users] Wiki Upgrade

Hi Everyone, The wiki has just been upgraded. Please let us know if there are any problems. Thanks, Ali ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] SPARC_SE -> Unimplemented Instruction

Hi Monir, As Jason mentioned this happens (on all ISAs) because of an unimplemented instruction. If you look at arch/sparc/isa/decoder.isa you’ll find a line like FailUnimp::for(). What is missing here is the implementation of the for instruction. You should be able to find a definition for it

Re: [gem5-users] BadgerTrap tool for ARM

Hi Nizam, While it’s true ARM has a hardware page table walker so does x86. There is a valid and a reserved bit in the page table descriptor just like on x86 so you should be able to play the same type of trick that BadgerTrap uses by using the reversed bit to cause a trap. Ali > On Sep 11,

Re: [gem5-users] Understanding the memory address in the trace

The address 0x81aa1a0 is a virtual address which is mapped to a physical address (very simply for sys call emulation). The bold addresses you’ve highlighted are physical addresses from the this mapping. Ali > On Dec 26, 2016, at 4:16 PM, ps4 lover wrote: > > Hello List, > > I am using the m

Re: [gem5-users] Aggressive debug file compression

Hi, I think that is a great idea if we can find code that is suitably licensed. The code that detects the .gz is in src/base/output.cc; look for OutputFile being instantiated. The code that is actually doing the compression is in ext/iostream3.We’d need a streambuf class that wraps LZMA Ali >

[gem5-users] Wiki updated

The wiki has been updated to the latest version of mediawiki. Everything appears to be working, but if you run into issues please let me know. Ali ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] video documentation

Hi Ben, These are great! Thanks for taking the time to create them. Could you find an appropriate place on the wiki and add the videos to the pages? One of the other things that comes up rather frequently is how to put new benchmarks on the disk image. You mention some ideas of how to do this

Re: [gem5-users] video documentation

dumped)" > # Also, specifying memory and CPU didn't help qemu-system-arm -m 1G -cpu arm926 disks/linux-arm-ael.img -kernel binaries/vmlinux.arm.smp.fb.2.6.38.8 > # I still get " Segmentation fault (core dumped)" > > Thanks, > > Ben > > PS: I added notes t

Re: [gem5-users] source code documentation

It's been updated to the latest version. Ali On 04.11.2012 01:37, Hossein Nikoonia wrote: > Dear All, > > I think doxygen-generated documents of source code is located in http://www.gem5.org/docs/index.html [1] > However, It's outdated. Is there a newer version somewhere online? > I know

Re: [gem5-users] compiling RAMSpeed benchmark in X86 full system mode

Hi Ben, See below. On Nov 7, 2012, at 1:57 PM, Payne, Benjamin wrote: > Hello, > > I'm interested in running the RAMSpeed benchmark > http://alasir.com/software/ramspeed/ > http://www.alasir.com/software/ramspeed/ramspeed-2.6.0.tar.gz > for x86, ideally for both syscall emulation mode and full

Re: [gem5-users] Cache Trace Understanding

Yes to both. Ali On Nov 6, 2012, at 6:14 PM, z...@uwaterloo.ca wrote: > Hi, > > I see, so what is the default write policy for default cache in gem5? Is it > write-allocate? or no write allocate? I'm assuming it's write-allocate with > writeback cache? > > The gem5 site only says "The defaul

Re: [gem5-users] LSQ in O3: Squash instructions when a load packet is rejected by cache

Hi Amin, I think it might work. Please feel free to implement it and see what happens. The only thing that might be an issue is something due to ordering, but I can't think of what that is at the moment. Thanks, Ali On 14.11.2012 12:19, Amin Farmahini wrote: > Hi All, > > In O3 LSQ, w

Re: [gem5-users] Memory opcodes: initacc, execute, competeacc?

Hi, Because the simple atomic CPU gets a response to memory accesses immediately it doesn't need a split transaction (init, complete). The other CPU models consider the timing of the memory system and therefore have to use split transactions. Thanks, Ali On 10.11.2012 21:10, Tri M. Nguye

Re: [gem5-users] ARM/O3: Load-linked, store-conditional behavior

I'll bug him and see if he's tested it out yet. > > On Thu, Oct 11, 2012 at 7:32 PM, Ali Saidi wrote: > >> Hi Mitch, >> >> Did you end up getting it working? >> >> Thanks, >> Ali >> >> On Sep 26, 2012, at 3:39 PM,

Re: [gem5-users] error setting --prog-interval

You need at specify a time.. 1 has no units. Ali On Nov 16, 2012, at 6:00 AM, Mahmood Naderan wrote: > Hi > In the lastest revision, when I use "--prog-interval=1" or > "--prog-interval 1" it says > > TypeError: wrong type '' should be str > Error setting param AtomicSimpleCPU.progr

Re: [gem5-users] Pass Kernel Parameters to gem5?

HI Joel, You should be able to pass parameters to the kernel by editing FSConfig.py. We already have to pass several parameters to the kernel to make it gem5 boot, so you should be able to easily add one. Ali On Dec 7, 2012, at 8:06 PM, Joel Hestness wrote: > Hey guys, > I'm wondering if it

Re: [gem5-users] Mismatching about L2 Configuration for ARM FS

A configuration register is read to get this value, and it's not changed to reflect the configuration you're actually simulating. It sholudn't matter, but feel free to change it. Ali On 13.12.2012 02:45, Yongbing Huang wrote: > Hi all, > > I set the associative of L2 cache to 16 in the c

Re: [gem5-users] tcmalloc checking failed

How did it fail? What does it say? Ali On Dec 18, 2012, at 5:14 AM, zhengchl wrote: > Hi, > > My os is Ubuntu 10.04 x86_64. And libgoogle-perftools-dev can't be installed > from official repository because of depend problems on ubuntu 10.04, so I > have to compile it myself. > > I think

Re: [gem5-users] Need help to solved Page table fault when accessing virtual address 0xf0000

You're accessing memory that doesn't exist probably because your application has a bug in it. Ali On Dec 18, 2012, at 2:03 AM, Musharaf Hussain wrote: > > > > Hi All > > Anyone can help me on below trace back? What is needed here to solve the > problem? > > 1. Panic:Page table fault when

Re: [gem5-users] tcmalloc checking failed

scons: `build/ALPHA_MOESI_CMP_directory/gem5.fast' is up to date. > scons: done building targets. > > On 12/18/2012 10:19 PM, Ali Saidi wrote: >> How did it fail? What does it say? >> >> Ali >> >> On Dec 18, 2012, at 5:14 AM, zhengchl wrote: >> &g

Re: [gem5-users] Ticks in GEM5

Maybe on the FAQ page? Ali On Dec 26, 2012, at 7:34 AM, "Payne, Benjamin" wrote: > Since this question gets asked often to the list, I looked on the gem5 wiki > for "tick" and "ticks" and didn't find any explanation (please let me know if > I missed it somewhere). > > I'd like to put an expl

Re: [gem5-users] gem5 versus MARSS

Hi Dave, There isn't a limit on the number of pending page walks. At least for ARM only a single walk can be active at a time. Because the walk does take time, back pressure is applied to the CPU, but the CPU can request as many as it would like. Since this original posting, a bug was fixed in

Re: [gem5-users] Weird behavior when running different [independent] workloads on multicores

I would guess the exit() call that hello world is performing is exitGroup not exit (I don't know why) which causes all threads to exit. Ali On 07.01.2013 09:03, Payne, Benjamin wrote: > Hello, > > Could you post the commands you are using to perform the tasks you describe? > > Also, if

Re: [gem5-users] Regarding changeset 9396

Hi Nilay, Do you have protoc installed, but pkg-config doesn't know about it? Thanks, Ali On 07.01.2013 17:42, Nilay Vaish wrote: > This changeset adds support for building with google protobuf. I think the > patch erroneously assumes that pkg-config will work correctly in all > situ

Re: [gem5-users] Gem5 Wrong Path Execution

Yes it does. Ali On 08.01.2013 14:38, MM wrote: > Hi, > > I was wondering if Gem5 does wrong path execution. > If yes, great! > If not, how does it estimate the effect of wrong path > execution on the IPC (and other performance metrics)? > > Thank you! > > ___

Re: [gem5-users] Fwd: Re: problem when use checkpoint in my program

HI Negar, This is a linking issue, something about how you specified the path to the parsec hooks isn't working, but it's not at all clear form the command line why, especially if as you say it worked for the other benchmarks. This is one of those things you're going to have to dig into the ou

Re: [gem5-users] Performance of the arm_detailed model

Hi Orangaede, I've seen a v8 benchmark run successfully to completion with the out-of-order model. That said it's possible that some part of your configuration is hitting a corner case that is causing issues. The various v8 benchmarks have different run times (i'm not sure which one you're talk

Re: [gem5-users] Running benchmark on FS X86 : Assertion `!delayedResponse' failed.

It appears as though the page table walker inserted a translation into the TLB and then when it came to use that translation it wasn't available (and would require another walk), which is causing the assert to happen. You should figure out what is being inserted and why it isn't matching in the

Re: [gem5-users] Performance of the arm_detailed model

tion PC:%s " "[tid:%i] [sn:%i].n", Ali On 09.01.2013 09:03, Ali Saidi wrote: > Hi Orangaede, > > I've seen a v8 benchmark run successfully to completion with the out-of-order model. That said it's possible that some part of your configuration is hitting a co

Re: [gem5-users] LD_LIBRARY_PATH & LIBRARY_PATH

Hi Kalai, I haven't seen that error before, but I'd guess it would might have something to do with how gcc was configured. You might want to turn on the verbose option (--verbose) and take a look at the command lines being generated by the linker. Additionally, you probably need to set LD_LIBR

Re: [gem5-users] LD_LIBRARY_PATH & LIBRARY_PATH

Hi Kalai, This I have seen before and is caused by python not being compatible with the libc that is in the LD_LIBRARY_PATH. Ali On 09.01.2013 17:37, Kalai Narayanan-SSI wrote: > Hi Ali, > > If I set LD_LIBRARY_PATH AND LIBRARY_PATH env variables, then executing results in: > > Trace

Re: [gem5-users] booting linux kernel 3.7 for ARM

Hi Chen, The source code to boot.arm is in system/arm/bootloader it's a very simple bootloader that just puts enough stuff in registers for the kernel to start. I haven' tried Linux 3.7, but we trap udelay so that we can skip the function in the simulator and just account for the time rather t

Re: [gem5-users] LD_LIBRARY_PATH & LIBRARY_PATH

2:48 PM To: sa...@umich.edu; gem5 users mailing list Subject: Re: [gem5-users] LD_LIBRARY_PATH & LIBRARY_PATH Hi Kalai, Just a thought...while you are busy making all the tools and libraries like each other, if you just want to get going, an Ubuntu 12 virtual machine only needs a single

Re: [gem5-users] booting linux kernel 3.7 for ARM

Hi Chen, You probably should start with one of the kernel config files available on the website on the download page. Otherwise, you'll need to use some debug flags to see what code is executing and where it is getting stuck in the boot process. Ali On 10.01.2013 16:31, Chen Tian wrote:

Re: [gem5-users] Checkpointing principle

Prior to some changes that will be committed soon it was possible for a CPU to stop in the middle of a micro-op for a checkpoint. Some changes on the review board change this functionality so it will only stop at instruction boundaries. Ali On 15.01.2013 14:33, Anouk wrote: > Dear, > > I

Re: [gem5-users] memory limit to ARM target

The VExpress platform supports 2047MB of memory. Ali On Jan 15, 2013, at 7:02 PM, Chen Tian wrote: > Hello, > > In FSconfig.py, there is a limit on memory size: > > if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): > print "The currently selected ARM platfo

Re: [gem5-users] memory limit to ARM target

memory). kernelStart 0x(c0008000) - kernelEnd 0x(c03839b4) > @ cycle 773564 > [initState:build/ARM/sim/system.cc, line 275] > Memory Usage: 773564 KBytes > tianc@tianc-testBox$ > > It looks like VExpress_EMM is the most promising one to execute. But I am getting this invalid lo

Re: [gem5-users] a question about internal implementation

Hi Chen, Please take a moment and write up a page on the wiki about what you found. I've seen the question before and I don't think we have any good documentation on it. Thanks, Ali On Jan 17, 2013, at 6:22 PM, Chen Tian wrote: > I am able to answer the question by myself. Thanks for any atte

Re: [gem5-users] ARM timer_cpulocal

Hi Dan, The kernel uses the timer and it's not generally accessible from user space. Ali On Jan 10, 2013, at 12:10 PM, Daniel wrote: > Is there any documentation for using the CPU Local Timer for ARM? I see that > there is a device in the src/dev/arm folder for it. > > 1. If I want to use it

Re: [gem5-users] ARM FS dual - drive sys kernel panic following checkpoint restore

Hi Stuart, There was a bug that was fixed last week that might fix this issue with how checkpoints for multiple systems memory images were tarn. Could you give the latest code a try? Thanks, Ali On Jan 3, 2013, at 5:38 AM, Stuart Ryan wrote: > Hi, > I am trying to run one of the example benc

Re: [gem5-users] LD_LIBRARY_PATH & LIBRARY_PATH

.py", > line 107, in > class Event(m5.internal.serialize.Serializable): > AttributeError: 'module' object has no attribute 'internal' > > -Kalai > > > From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On > Behalf O

Re: [gem5-users] Implementing DVFS on Gem5

Hi Guru, It's not possible to change the cpu clock from these registers. They're simply there to make the kernel or boot loader happy when it reads them. We have been working on implementing the ability to change the clock frequencies at run time in gem5 and you can see the new ClockedObjects i

[gem5-users] Position working on gem5 at ARM

ARM is looking to hire a motivated and skilled individual to work on gem5 full-time. Candidates must have outstanding C++ and Python skills, as well as previous experience with large software projects. Previous documented use and development with gem5 is ideal. This position is available either

Re: [gem5-users] ARM timer_cpulocal

ng for and much higher resolution than most timers. See http://www.gem5.org/M5ops Ali On Jan 21, 2013, at 3:37 PM, Daniel Lo wrote: > > Ali Saidi umich.edu> writes: > >> >> Hi Dan, >> >> The kernel uses the timer and it's not generally accessible f

Re: [gem5-users] how to write some variant into simulation‏

Take a look at http://www.gem5.org/M5ops as they might provide some of the functionality you're looking for. The other thing that might work for you is the PCEvent object which lets you trigger an event based on a PC value. Ali On Jan 21, 2013, at 7:45 AM, Konstantinos Parasyris wrote: > Sinc

Re: [gem5-users] Difference between the counters (functional vs performance)

Hi Orangeade, What about the misses per thousand instructions (E.g. device MSHR misses by instructions) for both models? Ali On Jan 22, 2013, at 6:59 AM, Mr. Orangeade wrote: > Hi guys, > > I'm trying to compare the values of the cache-related counters for the > functional and performance

Re: [gem5-users] Error when running bbench under arm_detailed

Hi Si, You're going to have to figure out where the invalid register index is coming from. It's only happening in the o3 cpu, because the simple CPU models don't rename registers like the o3 does. However, somewhere in there an invalid physical register file value is being generated. Hopefully

Re: [gem5-users] Understanding the dcache.overall_miss_rate in stat.txt

Hi Si, I imagine you're sampling multiple times? THe cpu.data vs switch_cpu.data is because the transition between CPU models when you restored from a checkpoint. I imagine the second switch_cpus is a another sample. Note you probably want overall_mshr_miss_rate. Thanks, Ali On 30.01.201

Re: [gem5-users] vldr instructions (add possibly others) can be (wrongly) considered as control instructions

The quickest thing I can think to do is everywhere that the test for intreg15/is_branch is done add something like && isFloating(). Ali On 01.02.2013 17:31, Nathanaël Prémillieu wrote: > Hi all, > > Patch http://reviews.gem5.org/r/1376/ [1] (changeset 9153) adds a test to > identify load

Re: [gem5-users] C library for python 2.7

What OS are you using? In many cases there is a python-dev or similar package you can install. Otherwise, you'd need to build python from scratch and configure it with the shared-lib option. See http://www.gem5.org/Using_a_non-default_Python_installation for more information. Ali __

Re: [gem5-users] memory management

Why should it be N*4GB? In each process using 4GB of memory? That doesn't seem right. I'd guess your issue is that a bad request is being generated somewhere in the memory system and making it incredibly large is just covering the problem up. Ali On Feb 2, 2013, at 2:57 AM, Mahmood Naderan w

Re: [gem5-users] C library for python 2.7

x27;m using Linux x86_64 - RHEL4 and have configured python2.7 with >--enable-shared option. My LD_LIBRARY_PATH points to libpython2.7.so. > >-Original Message- >From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On >Behalf Of Ali Saidi >Sent: Saturday,

Re: [gem5-users] C library for python 2.7

> >Thanks, >Uday > > > >-----Original Message- >From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On >Behalf Of Ali Saidi >Sent: Monday, February 04, 2013 4:27 PM >To: gem5 users mailing list >Subject: Re: [gem5-users] C library for p

Re: [gem5-users] Memory Initialization

Before the cpu starts executing the code in src/base/loader/* loads the binary into memory (the instructions) and the code in src/arch/**/process.cc builds up a stack frame as appropriate for the architecture/OS that you're simulating. Ali On 05.02.2013 18:22, Tao Zhang wrote: > Hi Yinchon

Re: [gem5-users] Possible Bad Invalidation in Cache Insert

The code is marking the block that is being replaced invalid there, and the caller of insertBlock() should be marking the block valid when it's the insertion is complete (along with the other status the block can have based on why the block is being replaced). Ali On Feb 7, 2013, at 6:07 PM,

Re: [gem5-users] telnet and m5term freezes

It looks like you have many copies of gem5 running. If you look at the output you can see that the version you pasted is listening for a terminal connection on port 3465. Ali On Feb 6, 2013, at 3:46 PM, mehmet basaran wrote: > Hi all (Apologies for the previous mail), > > I am trying to run

Re: [gem5-users] Resolve panic error

I would recommend you get the latest source and try again. The version you're running is about 6 months old. Ali On Feb 10, 2013, at 9:33 AM, Abu Saad wrote: > Hi all > > have any idea about the below problems? I want to run parallel program on > gem5.opt with se.py , it was running with s

Re: [gem5-users] C library for python 2.7

How can I force gem5's SConstruct to take this path while looking > for Python2.7? > > Thanks, > Uday > > -Original Message- > From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On > Behalf Of Ali Saidi > Sent: Wednesday, February 06, 2013 2:24

Re: [gem5-users] C library for python 2.7

2/02/2013 05:54, "Ranga, L Udaya" wrote: > >> Thanks Ali, >> >> That worked :) >> >> -Uday >> >> >> -Original Message- >> From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On >> Behalf Of Ali

Re: [gem5-users] Is it possible to use L2 prefetch with AtomicCPU?

You can use caches with the Atomic memory mode (and CPU). Generally people don't because the requests still aren't split transaction, but they will run in the system. As far as the prefetcher goes, I'm not certain the prefetcher is activated when the memory mode is set to atomic. You could look

Re: [gem5-users] TLB lookup functional mode not implemented

This should be fixed in the development repository as of a few hours ago. Ali On Feb 13, 2013, at 9:56 PM, mihai pricopi wrote: > Hello, > > I am trying to do a functional TLB entry search in FS mode without modifying > any state. > I am using the /arch/arm/tlb.cc TLB::lookup(Addr va, uint8

Re: [gem5-users] VExpress_EMM kernel sources

Take a look at http://gem5.org/Download Ali On Feb 15, 2013, at 9:49 PM, mihai pricopi wrote: > Hi, > > Does anyone know where can I obtain the kernel source used for compiling the > latest arm VExpress_EMM kernel image from the download page ? > I have tried to configure myself a linaro-

Re: [gem5-users] VExpress_EMM kernel sources

kernel source. > Is it somewhere on that page and I don't see it ? > > > On Sat, Feb 16, 2013 at 11:34 PM, Ali Saidi wrote: >> Take a look at http://gem5.org/Download >> >> Ali >> >> >> On Feb 15, 2013, at 9:49 PM, mihai pricopi wrote: >

Re: [gem5-users] physical page number at L2 accesses

I think you'll have to carry it from the TLB. Ali On Feb 19, 2013, at 1:40 AM, mihai pricopi wrote: > Hi, > > I am currently tracking the accesses at the L2 cache in an ARM FS > mode. I am extracting the physical address by calling the > pkt->getAddr() function > I am interested in the physica

Re: [gem5-users] vldr instructions (add possibly others) can be (wrongly) considered as control instructions

Hi Nathanaël, Did you try to implement this? Thanks, Ali On Feb 1, 2013, at 6:12 PM, Ali Saidi wrote: > The quickest thing I can think to do is everywhere that the test for > intreg15/is_branch is done add something like && isFloating(). > > > Ali > > >

[gem5-users] question/answer site http://qa.gem5.org

Hi Everyone, We've just created an question and answer site on http://qa.gem5.org. Hopefully with this site we can build a list of commonly asked questions and answers to them that is more easily searchable and allows users to find the information they're looking for much more quickly than sear

Re: [gem5-users] Newbie: Classic Memory Model

Hi, A answered your first question on our new question/answer website: http://qa.gem5.org/7/what-does-the-flow-through-the-classic-memory-system-look-like As far as the other questions, you can add a new identifier in packet.cc/hh and depending on it's purpose you'll have to use it in that

Re: [gem5-users] Count integer division instructions

On 21.02.2013 08:22, Mr. Orangeade wrote: > Hi guys, > > I'm trying to count integer division instructions (sdiv/udiv instructions from ARM ISA to be more specific). > I've added the following code to cpu/simple/base.cc: > > void > BaseSimpleCPU::postExecute() > { > . > if (curStaticInst

Re: [gem5-users] Final committed instruction count does not equal the sum of individual committed instruction counts

On 20.02.2013 16:55, Umesh Bhaskar wrote: > Hi all, > > I am trying to understand the various stats available in the stats.txt file for the Hello World binary under O3 configuration. > Specifically, I am looking at the folder /tests/quick/se/00.hello/ref/arm/linux/o3-timing. > > Here the

Re: [gem5-users] [KVM-ARM] Simulator Support

gem5 doesn't currently support the ARM virtualization extensions, so you won't be able to run a KVM enabled kernel on gem5. Ali On Feb 22, 2013, at 1:41 PM, sanju james wrote: > > > > Hallo, > > I am master student, am doing some research with Linux-kvm on Arm cortex a-15 > for versatile

Re: [gem5-users] read ARM CCNT register

Hi Fangfei, I don't know that the ccnt register is implemented for ARM at the moment. You can probably get what you want by executing the pseudo instruction rpns() (see util/m5/m5oph.h). Ali On Feb 23, 2013, at 12:09 AM, Fangfei Liu wrote: > Hi, > > Does anyone know whether it is possible

Re: [gem5-users] gem5 abort restoring X86 detailed mode

Hi Gedare, The right place is bugs is http://flyspray.gem5.org however this bug should be fixed with this patch: http://reviews.gem5.org/r/1741/ Ali On 25.02.2013 14:20, Gedare Bloom wrote: > Hi, > > Is this the right place to submit bug reports? > > When I restore with the detailed cp

Re: [gem5-users] Alpha In-Order CPU Model is not working well

If memory serves the change breaks the o3 cpu for Alpha. Ali On 26.02.2013 08:41, Anthony Gutierrez wrote: > Can we push that patch out? > > Anthony Gutierrez > http://web.eecs.umich.edu/~atgutier [4] > > On Tue, Feb 26, 2013 at 8:39 AM, WonSeob Jeong wrote: > >> Hi, Korey >> >> Th

Re: [gem5-users] vldr instructions (add possibly others) can be (wrongly) considered as control instructions

plemented. > And for the moment, I don't really have the time to work on the solution you > have proposed. > > Thanks, > Nathanaël > > Le 19/02/2013 14:04, Ali Saidi a écrit : >> Hi Nathanaël, >> >> Did you try to implement this? >> >

Re: [gem5-users] Compiling on OS X 10.8.2

HI Tony, I'm running 10.8.2 and didn't install gcc via macports. I installed the command line Xcode only. With that I can compile with g++ (which is a modified version of 4.2). Somehow this version passes the check and compiles even though normal gcc wouldn't (I believe because of the llvm back

Re: [gem5-users] Internet connection inside of gem5 simulator

Hi Jinchun, There isn't a way to have gem5 connect to the internet. You can connect multiple simulations together, but if you want to get some benchmarks like this you should put them on the disk image, run a client and a server and connect them via an EtherLink object. Ali On Feb 28, 2013, a

Re: [gem5-users] How to dump data structure symbols to trace files ?

Hi Umesh, inUserMode is checked because we don't have any access to symbols from user applications, on the kernel. So if we're executing some user mode code, we shouldn't be printing symbols because there is no chance we have some. There could be a bug with how we load the symbols for kernel mo

Re: [gem5-users] panic: Error opening /dist/m5/system/disks/linux-parsec-2-1-m5.img

Hi Tejas, You need to masure that you have read access to the /dist/m5/system/disks/linux-parsec-2-1-m5.img file and that directory exists. It's almost certainly the case that you don't. Thanks, Ali On Feb 26, 2013, at 11:27 PM, tejasi pimpalkhute wrote: > Hi, > > I am trying to run Parsec

Re: [gem5-users] Multiple CPUs not recognized by program

HI Jordan, Did you ever make any progress with this? What does /proc/cpuinfo say? Ali On Feb 25, 2013, at 5:15 PM, Jordan Fix wrote: > Hello, > > I'm booting into full system mode with 4 processors and running a test > program which calls: > > sysconf(_SC_NPROCESSORS_ONLN); > > to determin

Re: [gem5-users] Why the number of instructions is very different between using timing and detailed ?

The simple cpus models access the cache for every instruction, while the o3 model accesses the cache a line at a time and keeps that line in a buffer. If you're in a tight loop that stays in that buffer it won't fetch. Ali On Mar 5, 2013, at 5:23 AM, Maxime Chéramy wrote: > Hello, > > I am u

Re: [gem5-users] How to dump data structure symbols to trace files ?

; ExecSymbol value : 1 > debugSymbolTable->findNearestSymbol returns string: > inUserMode returns : 1 > : ldr r12, [pc, #36] : MemRead : D=0x8960 A=0x817c > 34000: system.cpu T0 : 0x8154 @ > debugSymbolTable value : 0x2f48340 > ExecSymbol value : 1 >

Re: [gem5-users] Classic cache aliasing and hashing

Hi Erik, It doesn't, but memory allocation is pretty dump in SE mode. VA -> PA, so it's certainly possible you're getting into a case where lots of things conflict. Ali On 12.03.2013 16:27, Erik Tomusk wrote: > Hello All, > > Does the classic memory model do any sort of address hashing

Re: [gem5-users] Classic cache aliasing and hashing

em5 that might be causing the cache to miss? I've ruled out the compiler doing anything strange. > > Thanks, > Erik > > On 12/03/13 18:26, Ali Saidi wrote: > >> Hi Erik, >> >> It doesn't, but memory allocation is pretty dump in SE mode. VA -&g

Re: [gem5-users] '-I' option in FS mode

yes it includes all instructions. Ali On Mar 17, 2013, at 4:53 AM, hanfeng QIN wrote: > Hi all, > > If I run gem5 in FS mode, I specify the maximum instruction count to be > simulation by '-I' option. However, does the maximum instruction count > contain instructions from the operating syste

Re: [gem5-users] How can I set server-client configuration?

Hi, The messages printed aren't necessarily an error. The kernel can't find any modules to load, however, if what it needs is built into the kernel it doesn't have to. It's looking for thinks like the tcp/ip stack which is probably built in. Ali On Mar 22, 2013, at 7:36 AM, Jinchun Kim wrot

Re: [gem5-users] How can I set server-client configuration?

That is the most likely issue. Does your configuration include an ethernet device (e.g. igbe_e1000)? Does your kernel have the e1000 driver? Thanks, Ali On Mar 22, 2013, at 4:09 PM, Jinchun Kim wrote: > Thanks Ali. > However, when I tried to configure eth0 by > ifconfig eth0 $SERVER txqueuele

Re: [gem5-users] about CoherentBus() parameters?

Take a look at src/mem/Bus.py. CoherentBus inherits from Bus so all those parameters are available as well. Ali On Mar 21, 2013, at 8:02 PM, "Alshamlan, Mohammad" wrote: > Hi all, > > I know just two parameters for CoherentBus() which are: > CoherentBus(clock="1GHz", width = 16). I'm wonderin

Re: [gem5-users] Triggers to start or stop collecting instruction traces?

There isn't any support for this at the moment, but you could add it. If you know the cycle in which your benchmark is going to run you can also start collection with --trace-start=. Ali On Mar 13, 2013, at 10:08 PM, huangyongbing wrote: > Hi all, > > I want to collect instructio

Re: [gem5-users] How to get the task_struct entry under arm platform?

Generally if you want to do this you can setup a PCEvent on __switch_to in the kernel and you'll know at that point what the user code that is about to execute is going to be. Ali On Mar 14, 2013, at 2:29 AM, huangyongbing wrote: > Hi all, > > I want to get the task_struct entry of

Re: [gem5-users] How can I set server-client configuration?

There are two separate issues here, the first is making sure that the device is included in the gem5 configuration and it look like with the default configuration files this is not the case for x86, so you should add it. After that you'll notice if the device is recognized by the linux kernel y

Re: [gem5-users] Statistics per quantum - Simulation.py

Hi Balaji, You're correct, it's ply called once. If you'd like to reschedule a repeating event, you'll need to do something to make that happen. Some possibilities include changing the LocalSimLoopExitEvent to re-schedule itself after it's executed, create a parameter that does this, or create

Re: [gem5-users] Instrument a program with gem5

Hi David, It's certainly possible, but it's going to take some work. My random idea would be to change how all the branch instructions are defined, so the stash their real target address somewhere and jump to your handler. Other than that manually instrumenting the program (or doing it with som

Re: [gem5-users] How to adjust the window size of VNC

The code you're pointing to specifies the max size for the lcd controller. If you want to change the size of the vnc window you need to change the size of screen that you're simulating (e.g. pass different parameters to the kernel on boot). Ali On Mar 25, 2013, at 3:10 AM, "huangyongbing" wr

Re: [gem5-users] bind application to cores

Where the instruction counts on the cores the same? If the application was small enough the instruction and ilc might be dominated by the system booting. Ali On Apr 9, 2013, at 9:54 PM, Hui Zhao wrote: > I am running a parsec benchmark with 4 threads on 4 core Alpha FS machine, I > used "m5 p

Re: [gem5-users] --script option not working

If you use a unmodified m5/m5.c binary the problem doesn't occur? What changes did you make to the binary, I'd guess that changed something. The other thing to check is that the simulator has permission to read the file you put on the command line. You also might want to try an absolute path in

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