Hi Si,
I imagine you're sampling multiple times? THe cpu.data vs switch_cpu.data is because the transition between CPU models when you restored from a checkpoint. I imagine the second switch_cpus is a another sample. Note you probably want overall_mshr_miss_rate. Thanks, Ali On 30.01.2013 09:35, Si Chen wrote: > Hi all, > > I am running bbench on arm detailed mode. But I have some trouble of understanding the stat results. I found that there are five different values in the stat for the dcache.overall_miss_rate. > > system.cpu.dcache.overall_miss_rate::switch_cpus.data 0.163675 # miss rate for overall accesses > system.cpu.dcache.overall_miss_rate::cpu.data 0.333333 # miss rate for overall accesses > system.cpu.dcache.overall_miss_rate::total 0.163678 # miss rate for overall accesses > system.cpu.dcache.overall_miss_rate::switch_cpus.data 0.065822 # miss rate for overall accesses > system.cpu.dcache.overall_miss_rate::total 0.065822 # miss rate for overall accesses > > What is the difference between them? Which one should I refer to as the overall miss rate? Why there are two entirely different total dcache.overall_miss_rate? > > Thanks, > Si > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1] Links: ------ [1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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