Hi Nathanael,

If you get a chance could you see if this patch http://reviews.gem5.org/r/1740/ 
fixes the problem you encountered?

Thanks,
Ali


On Feb 19, 2013, at 7:26 AM, Nathanaël Prémillieu 
<nathanael.premill...@irisa.fr> wrote:

> Hi Ali,
> 
> I have not try to implement that, I still have my bad solution implemented.
> And for the moment, I don't really have the time to work on the solution you 
> have proposed.
> 
> Thanks,
> Nathanaël
> 
> Le 19/02/2013 14:04, Ali Saidi a écrit :
>> Hi Nathanaël,
>> 
>> Did you try to implement this?
>> 
>> Thanks,
>> Ali
>> 
>> On Feb 1, 2013, at 6:12 PM, Ali Saidi <sa...@umich.edu
>> <mailto:sa...@umich.edu>> wrote:
>> 
>>> The quickest thing I can think to do is everywhere that the test for
>>> intreg15/is_branch is done add something like && isFloating().
>>> 
>>> 
>>> Ali
>>> 
>>> 
>>> On 01.02.2013 17:31, Nathanaël Prémillieu wrote:
>>> 
>>>> Hi all,
>>>> 
>>>> Patchhttp://reviews.gem5.org/r/1376/  (changeset 9153) adds a test to
>>>> identify load as control instructions if it write to the PC register.
>>>> But VLDR (vector load, floating point instruction) (and possibly others
>>>> instructions) are constructed using the same code. If this instruction
>>>> write to the FP reg 15, then its _dest variable is 15 (= INTREG_PC),
>>>> then the instruction is marked as being a control instruction, which is
>>>> wrong (I believe there is no floating point branch instruction).
>>>> 
>>>> However, I don't really know how to correct that as this part of the
>>>> instruction generator is quite obscure for me.
>>>> For the moment, I will just add a test that check if the control flag
>>>> and the floating point flag are set and disable the control flag in that
>>>> case. But it is not a good solution :)
>>>> 
>>>> Does anyone have an idea on how to correct that?
>>>> 
>>>> Nathanaël
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