Hi Nathanaël, Did you try to implement this?
Thanks, Ali On Feb 1, 2013, at 6:12 PM, Ali Saidi <sa...@umich.edu> wrote: > The quickest thing I can think to do is everywhere that the test for > intreg15/is_branch is done add something like && isFloating(). > > > Ali > > > On 01.02.2013 17:31, Nathanaël Prémillieu wrote: > >> Hi all, >> >> Patch http://reviews.gem5.org/r/1376/ (changeset 9153) adds a test to >> identify load as control instructions if it write to the PC register. >> But VLDR (vector load, floating point instruction) (and possibly others >> instructions) are constructed using the same code. If this instruction >> write to the FP reg 15, then its _dest variable is 15 (= INTREG_PC), >> then the instruction is marked as being a control instruction, which is >> wrong (I believe there is no floating point branch instruction). >> >> However, I don't really know how to correct that as this part of the >> instruction generator is quite obscure for me. >> For the moment, I will just add a test that check if the control flag >> and the floating point flag are set and disable the control flag in that >> case. But it is not a good solution :) >> >> Does anyone have an idea on how to correct that? >> >> Nathanaël >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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