Hi Nizam, While it’s true ARM has a hardware page table walker so does x86. There is a valid and a reserved bit in the page table descriptor just like on x86 so you should be able to play the same type of trick that BadgerTrap uses by using the reversed bit to cause a trap.
Ali > On Sep 11, 2016, at 6:03 AM, Nizamudheen Ahmed <nizam.ah...@gmail.com> wrote: > > Hi, > > I came across the BadgerTrap tool > (http://research.cs.wisc.edu/multifacet/BadgerTrap/ > <http://research.cs.wisc.edu/multifacet/BadgerTrap/>) that traps TLB misses > for x86 architecture. > > I could not locate similar tool for ARM architecture. Do you folks know if > such tool exists for ARM architecture? I would like to analyze TLB miss > pattern for "large" applications. I prefer to do this on AR Silicon. I > require BadgerTrap kind of tool to get me the data. > > > > I guess, the ARM architecture inherently does not support fault generation on > TLB misses. One could realize this by alternate means. One way that i thought > of was the following > > 1. Setup the TCR_EL1.EPD0/EPD1 bit to disable walk on TLB miss. > 2. On a TLB miss, a F_TRANS exception is raised. I guess this exception will > force Linux kernel to invoke the do_page_fault function. > 3. In that function if TCR_EL1.EPD0/EPD1 is set to disable walk on TLB miss, > i will temporarily enable it to allow this specific TLB fill. And, post > "this" fill, i should disable it again to "trap" next TLB miss. > > This solution should work okay, except the fact that my code will not be able > to intervene after the "this" fill. Any suggestion for this one champs? > > BR/Nizam > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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