[USRP-users] starting radios in parallel

I have a project where I have to start up a series of N320 radios.  Currently we do it sequentially and that can take some time.  Is there a way to do them in parallel? I thought I saw somewhere that the driver was the limiting factor for being able to have separate threads start up the devices

[USRP-users] Possible to change the name of an N320?

I have a series of N320s sprinkled across our lab and I would like to change their names so it is clear where they are located (as opposed to keeping a list of which serial number is where), is this possible? i could have sworn I could do this with a different Ettus device in the past, but I ca

[USRP-users] Re: Possible to change the name of an N320?

#x27; > > \[INFO\] \[MPM.Rhodium-1\] init() called with args > \`fpga=XG,mgmt_addr=192.168.10.2,product=n320,clock_source=internal,time_source=internal' > > Fetching current settings from EEPROM... > > Cannot find value for EEPROM\[name\] Neel Pandeya wrote: > Hell

[USRP-users] Re: Possible to change the name of an N320?

Marcus, the problem is that /etc/hostname gets overwritten on boot. I am guessing it is baked in somewhere else and gets populated on boot up. ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lis

[USRP-users] Re: Possible to change the name of an N320?

I am using static, so it isn’t a DHCP issue. I tried to use hostnamectl, and it did “work.” But after a reboot it was back to the default name. ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@l

[USRP-users] Re: Possible to change the name of an N320?

Bingo! This was it.\ The file was actually located in “/sbin” but I could see that it first checks for a file called /data/network/hostname. If it is present, it sets the hostname to whatever is in that file. If it isn’t there, it does the default hostname. I created the file and on reboot it

[USRP-users] Dropped samples in sync across channels?

I wanted to verify something to make sure I understand how things work. It seems to me that when using an X310 or N320 (the two USRPs I happen to be messing with), that when I am using both RX channels, if I change frequencies on on one channel, both will produce time tags in Gnu Radio. I’ve l

[USRP-users] Re: N320 sample rate change locking-up

Thanks Marcus. I agree, there is no way this is design-intent. My gut says it is some sort of clock situation on the FPGA, but I am not sure what. Unfortunately, the only ones who can probably weigh in on this would be some of the Ettus FPGA designers, and I am guessing that they don’t see to

[USRP-users] Re: N320 sample rate change locking-up

Marcus D. Leech wrote: > Sample-rate is an inherent property of a *stream* as I recall, rather > than a *session*.  Are you creating a new stream >   across sample-rate changes, or applying the rate change to an > existing stream? That is an interesting comment. I am not stopping and starting a

[USRP-users] Re: N320 sample rate change locking-up

OK, thanks. I was hoping that you were on to something. Thanks. ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com

[USRP-users] Re: time tags seem don't seem to match sample count

Thank you Marcus, that is helpful. I have restricted my testing to just an N320, and only freq changes for now.  I have run across something else that is odd though (but has major ramifications for my blocks).  Most of the time there are no drops and everything is fine, but here is an example o

[USRP-users] Troubles with the QSFP+ on the N3x0 series

I have been away from USRPs for a while but am back to using some N3x0 units and am having some issues. 1 - Does QSFP work with UHD 3.15? We'd prefer not to go up to v4 yet due to some issues we've seen in testing it, but I am not sure how well supported QSFP is on 3.15. 2 - When using the QS

[USRP-users] Re: Troubles with the QSFP+ on the N3x0 series

be ip based. Lastly. If we go the pure Aurora route, I know that we lose white rabbit, but we gain a full 40Gbps, right? Thanks again. On Jun 4, 2021, 4:18 PM, at 4:18 PM, Michael Dickens wrote: >Hi Jason - Answers, and more. I hope this is useful and helps clarify >the >options. - MLD &

[USRP-users] Re: Troubles with the QSFP+ on the N3x0 series

documentation is just that certain devices are Aurora capable, and not much else to go on. TIA. From: Michael Dickens Sent: Friday, June 4, 2021 5:00 PM To: Jason Matusiak Cc: Ettus Mail List Subject: Re: [USRP-users] Troubles with the QSFP+ on the N3x0 series

[USRP-users] Re: Troubles with the QSFP+ on the N3x0 series

soon, but for now that’s about all I have. Hope this is helpful. On Jun 9, 2021, at 09:14, Jason Matusiak wrote:  Thank you for all the info Michael. Are you aware of any examples/writeups/tutorials of USRPs and Aurora in action? I am trying to wrap my head around how it is intended

[USRP-users] USRP X410 Transmitted signal distortion

coefficient. The obtained cross-correlation coefficient is not a simple peak, as shown in the annex. If x310 is used to transmit and x410 or x310 is used to receive, there is no such problem. UHD version: v4.1.0.2-rc3. The file system of x410 has also been updated to v4.1.0.2-rc3 Best regards, Jason

[USRP-users] pin definitions of the two HDMI interfaces of x410

Hi dear Engineers of Ettus Research, We plan to design a peripheral circuit board controlled by GPIO of x410. Now I would like to know the pin definitions of the two HDMI interfaces of x410. could you share relevant information? Best regards, Jason

[USRP-users] In-place Local Clock Update

Hi All, I’m currently working to synchronize multiple X310’s clocks without a PPS input, however right now the best method I can find to update the clock from a host PC (using the C++ API) is to query the current time from the USRP device (using usrp::multi_usrp::get_time_now), add a time delta

[USRP-users] Re: In-place Local Clock Update

e possible on the FPGA, but I’m wondering if this is possible via existing means in the UHD API, or if it may be implemented using custom RFNoC blocks somehow. Thanks again, Jason > On Dec 8, 2021, at 3:29 PM, Rob Kossler wrote: > > Hi Jason, > A few questions: > - why do you wa

[USRP-users] X310 based programs cannot run stably for a long time

n uint64_t ctrl_iface_impl<_endianness> :: wait_for_ack(bool,double)[with uhd :: endianness_t_endianness = uhd::ENDIANNESS_BIG;uint64_t = long unsigned int] at/home/xxx/uhd_3.15.0/uhd/host/lib/rfnoc/ctrl_iface.cpp:151 Is there a solution? Best regards, Jason __

[USRP-users] Re: X310 based programs cannot run stably for a long time

error mentioned in the last email. Best regards, Damon From: Marcus D. Leech Sent: Tuesday, January 11, 2022 3:46 AM To: usrp-users@lists.ettus.com Subject: [USRP-users] Re: X310 based programs cannot run stably for a long time On 2022-01-10 14:37, jason pro

[USRP-users] USRP X310 with UBX-160 and TwinRX

Hi all, We plan to use a x310 with a UBX-160 and a TwinRX to realize the system of one TX channel and two RX channels. The TX channel is provided by UBX and the two RX channels are provided by TwinRX. Does UHD driver support this configuration? Best regards, Jason

[USRP-users] RuntimeError: fx3 is in state 5

? Best regards, Jason ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com

[USRP-users] Error: rpc::timeout: Timeout of 2000ms while calling RPC function 'supports_feature'

C PLL Locked! [INFO] [MPM.Rhodium-0.init] JESD204B Link Initialization & Training Complete [INFO] [MPM.RPCServer] RPC server ready! [INFO] [MPM.RPCServer] Spawning watchdog task... Error: rpc::timeout: Timeout of 2000ms while calling RPC function 'supports_f

[USRP-users] Re: RuntimeError: fx3 is in state 5

Hi Marcus, Thank you for your reply. The image file we use is a standard image file from Ettus Research, which has not been modified. We have several pcs of B200mini-i, and only one device reports this error. Best regards, Jason From: Marcus D. Leech Sent

[USRP-users] Re: RuntimeError: fx3 is in state 5

Hi Marcus, This board was bought a year ago, so it is out of warranty. Is the FPGA chip broken? Best regards, Jason From: Marcus D Leech Sent: Tuesday, July 12, 2022 3:29 AM To: pro jason Cc: USRP-users@lists.ettus.com Subject: Re: [USRP-users] RuntimeError

[USRP-users] weird usrp coredump

Trying to run a C++ based flowgraph and occasionally getting a segfault/coredump. Finally, was able to capture the stack trace, and I am not sure what to make of it. I //think// that this is all UHD, and not my app, but I find that hard to believe. Here is that core dump, any thoughts on what

[USRP-users] Re: weird usrp coredump

Thanks guys, that makes sense. This was build against a GR and UHD that I installed via PyBombs, so I think I am OK on that front. It is pretty random, so I don't think I have a steady memory leak, but it easily could be something I am doing on my end. I'll try to keep a closer eye on it. _

[USRP-users] Properly changing tx_streamer channels

on solving the issue described above, or how to accomplish this in a different way, I would greatly appreciate the feedback. Thanks in advance, Jason ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usr

[USRP-users] N320 sample rate change locking-up

Are there any restrictions, or known issues, with changing the sample rate on an N320 while it is running? While debugging an issue in our application, we noticed that we can toggle between two sample rates and get the n320 to lock up. What I mean is that the N320 is still responsive to comman

[USRP-users] MPM startup failure on X410

is on the device in order to get it to work. Thanks. Jason ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com

[USRP-users] Re: MPM startup failure on X410

On 2/9/23 10:58, Marcus D. Leech wrote: On 09/02/2023 07:43, Jason Roehm wrote: I have an X410 device that I'm trying to update for use with UHD v4.4.0. It hasn't been used for a while, so at least several releases ago. I followed the procedure in the X410 manual (https://files

[USRP-users] Re: MPM startup failure on X410

On 2/9/23 13:23, Jason Roehm wrote: On 2/9/23 10:58, Marcus D. Leech wrote: On 09/02/2023 07:43, Jason Roehm wrote: I have an X410 device that I'm trying to update for use with UHD v4.4.0. It hasn't been used for a while, so at least several releases ago. I followed the proced

[USRP-users] time tags seem don't seem to match sample count

I have been trying to work on a gnuradio block to fill in the dropped samples in a USRP stream. While testing things out, I came across something odd. I am using an X310 as my test device and am changing the sample rate. I was at 100Msps, let it run for some time, and then changed it to 10Msp

[USRP-users] using VHDL modules in an RFNoC block

I have some code from a previous coworker that I would like to take advantage of. Currently it is VHDL and their top block (which I am calling), has things like: USE WORK.TYPES.ALL; USE WORK.HARDWARE.ALL; USE WORK.MATH.ALL; USE WORK.UTIL.ALL; USE WORK.FILTERS.ALL; USE WORK.RESAMPLERS.ALL; I un

[USRP-users] RFNOC OOT module no longer building

I added a new block to my OOT module and now when I run make from the build directory things don't build properly. I source my setup_env.sh and then run make from build and see the following: -- PyBOMBS installed GNU Radio. Setting CMAKE_INSTALL_PREFIX to /home/jmat/rfnoc -- Build type not spe

Re: [USRP-users] RFNOC OOT module no longer building

I think I solved this by blowing away everything within the testbench directory. I am not sure what happened, but this seems like the best fix for now. On 07/07/2017 12:04 PM, Jason Matusiak wrote: I added a new block to my OOT module and now when I run make from the build directory things

Re: [USRP-users] rfnoc-modtool cores

t OOT repos. If you have a suggested improvement that's less hacky though, I'm definitely interested :) EJ On Wed, Jun 14, 2017 at 2:08 PM, Jason Matusiak mailto:ja...@gardettoengineering.com>> wrote: EJ, I am creating a new RFNoC repo and thought I would go through your

[USRP-users] ERROR_CODE_BAD_PACKET

I am splitting one of my RFNoC blocks into two different ones, and one of them is giving me issues. The block is essentially a keep m in n block, so I only spit out data once in a while. This worked fine when combined with my other block, but now when I run it independently, it is throwing th

Re: [USRP-users] ERROR_CODE_BAD_PACKET

s doing vectors (it would be 4*PKT_SIZE), should I do something different there for a stream? On 07/10/2017 01:09 PM, Marcus Müller wrote: Sounds like the header might have not been adapted 100% correctly. Check whether your noc shell has the right fields set. Cheers, Marcus On 10 July 2017 7:03:5

[USRP-users] RFNoC timing clarification

I have a timing question that has me going in circles, I don't understand how the USRP timestamps work when using RFNoC. In a normal system, packets have timestamps with them (or at least the first one does) and you can compute the time of any samples based on the timestamp, sample rate, and n

Re: [USRP-users] RFNoC timing clarification

e into the block != the sample rate leaving the block in this case. ~Jason On 07/12/2017 12:58 PM, Jonathon Pendlum wrote: Hey Jason, The timestamp of each packet describes the time the first sample in the packet was received. The timestamp is based on a counter in noc_block_radio_core (timekeepe

[USRP-users] does an RFNoC block HAVE to have an input and an output?

I have a block that I want to essentially be a source block in RFNoC (outputting data from a ROM), but when I go to probe, I get this error: RuntimeError: LookupError: Path not found in tree: /mboards/0/xbar/dataGenerator_0/ports/in Is this because I set it up without sink input? Is there any

Re: [USRP-users] does an RFNoC block HAVE to have an input and an output?

_ettus_swig.device3_make(*args, **kwargs) RuntimeError: EnvironmentError: IOError: Block ctrl (CE_00_Port_30) packet parse error - EnvironmentError: IOError: Expected SID: 02:30>00:00 Received SID: 00:00>00:00 >>> Done On 07/13/2017 03:15 PM, Jason Matusiak wrote: I have a bloc

Re: [USRP-users] does an RFNoC block HAVE to have an input and an output?

wrote: Hey Jason, All blocks have to have at least 1 input and 1 output port. You are correct that you should still setup an input port in Noc Script, but not expose it in the GRC XML. Take a look at the Siggen block's HDL, Noc Script, and GRC XML. Jonathon On Thu, Jul 13, 2017 at 12:

[USRP-users] problem with RFNoC probing

I am not sure what is going on, but while working on my new RFNoC block, I can't probe my X310 anymore. When I do, I get this error: [INFO] [CORES] Performing timer loopback test... [ERROR] [UHD] Exception caught in safe-call. in virtual ctrl_iface_impl::~ctrl_iface_impl() at /home/jmat/rfn

Re: [USRP-users] problem with RFNoC probing

sure what all gets executed in Verilog when the probe occurs. On 07/17/2017 03:36 PM, Jason Matusiak wrote: I am not sure what is going on, but while working on my new RFNoC block, I can't probe my X310 anymore. When I do, I get this error: [INFO] [CORES] Performing timer loopback test

Re: [USRP-users] problem with RFNoC probing

Ah, that does sound like the issue. How do i know it is done initializing? You dont do something similar in the siggen block thoigh, right? Sent from my Verizon, Samsung Galaxy smartphone Original message From: Jonathon Pendlum Date: 7/19/17 5:34 PM (GMT-05:00) To: Jason

[USRP-users] timout issue on RFNoC output

I am still struggling with my "output only" RFNoC block and can't seem to figure out what silly thing I am doing wrong. I am generating data by reading from a ROM and can see it happening by monitoring the o_tdata (etc) lines coming from my lower module. If I look in my noc_block_dataGenerator

Re: [USRP-users] timout issue on RFNoC output

I need to re-setup my debug messages to check. To be clear, you are talking about the o_tdata (etc) up in my upper level noc_block_dataGenerator, right? On 07/21/2017 02:52 PM, Jonathon Pendlum wrote: Here is what should happen on the axi stream bus to the crossbar. You should first see the

Re: [USRP-users] timout issue on RFNoC output

ing the throttle helps, and what is special about running it the second time. Also, why will it "run" on a fresh boot, but when I probe it first it gets into a weird state? On 07/24/2017 12:32 PM, Jason Matusiak wrote: OK, in my original email I said that nothing was coming out of o_tdat

Re: [USRP-users] timout issue on RFNoC output

a good idea to add a sr_write to turn off the enable in your block's destructor code too. On Mon, Jul 24, 2017 at 10:29 AM, Jason Matusiak mailto:ja...@gardettoengineering.com>> wrote: One last piece of oddball info I've discovered. RFNoC:dataGenerator -> RFNo

Re: [USRP-users] timout issue on RFNoC output

Jonathon, I have been working on this the last two days and can't seem to get it working. My destructor looks like this: dataGenerator_impl::~dataGenerator_impl() { std::cout << "In here3.\n"; uhd::rfnoc::dataGenerator_block_ctrl temp; temp.issue_stream_cmd(::uhd::stream_cmd_t::S

[USRP-users] reducing RFNoC sample rate simpler?

I have an RFNoC block that is probably going to take in a vector of data (200msps off the RFNoC:Radio), sum it with some values and continue. Every X number of vectors (could be as high as 1024 times), it will output a vector of its own. This means that at 200msps, I could have a flow of data

Re: [USRP-users] RFNoC:Delay block?

Nick, I had worked on something similar (a keep m-in-n block actually), and may have oversimplified things. I kept track of how many samples I outputted and set the tlast accordingly, wouldn't that solve the "reconstituting packet boundaries" issue you mentioned? Also, I am not sure I investi

Re: [USRP-users] reducing RFNoC sample rate simpler?

rate. Everything works fine because UHD has no expectations on the line rate of the incoming data stream. On Tue, Aug 8, 2017 at 12:02 PM, Jason Matusiak via USRP-users mailto:usrp-users@lists.ettus.com>> wrote: I have an RFNoC block that is probably going to take in a vector of da

Re: [USRP-users] Building FPGA image

I've done it many times. When you open it and you do a save-as of the project, make sure that you don't check the option box to copy the files over, you want to leave them in their current location. On 08/16/2017 10:15 AM, Torres Figueroa, Luis Angel via USRP-users wrote: Hi folks, Has som

Re: [USRP-users] Building FPGA image

uis Angel wrote: Hi Jason, It worked. I downloaded the source files from rfnoc-devel branch in the repository again and build it without choosing the option you mentioned. I have still some critical warnings, but the image has been correctly generated and I could use it in the URSP. Also,

[USRP-users] problem with RFNoC block not outputting

I have a block that I've been working on and it seems like I am missing something vital to get it to work properly. My block takes in a vector of 2048 samples and outputs 2048 samples as well. I simulated it and it passes simulation fine. But, if I look at the output as it goes to a file, no

Re: [USRP-users] problem with RFNoC block not outputting

. On 09/11/2017 02:05 PM, Jason wrote: I have a block that I've been working on and it seems like I am missing something vital to get it to work properly. My block takes in a vector of 2048 samples and outputs 2048 samples as well. I simulated it and it passes simulation fine. But, if I

Re: [USRP-users] problem with RFNoC block not outputting

? Is it an Ethernet frame issue? I feel like somewhere back in the day I heard that all the data needs to fit into a frame size, so maybe 1024 is a max frame size in this case... On 09/11/2017 03:06 PM, Jason wrote: One other piece of information. It seems like I always get hung up on the

Re: [USRP-users] Quad channel receiver operation of B210

Sumit, There is a T/R switch between the TX/RX and RX2 ports, so you can only use one at a time for each channel. On 09/15/2017 01:17 PM, Sumit Kumar via USRP-users wrote: I asked because the TX/RX port can also be used as RX right. That's why I had the perception that all 4 ports can be used

[USRP-users] the rfnoc fifos

OK, dumb question, but I just can't come up with a good answer.  I understand that the RFNoC FIFOs are a must if you only have one NoC block that you want to use and are using the GNURadio host [1].  So why do pretty much most of the examples ALWAYS have at least one, and why would I want to fi

Re: [USRP-users] the rfnoc fifos

via USRP-users wrote: On Wed, Sep 27, 2017 at 01:42:22PM -0400, Jason Matusiak via USRP-users wrote: OK, dumb question, but I just can't come up with a good answer.  I understand that the RFNoC FIFOs are a must if you only have one NoC block that you want to use and are using the GNURadio

[USRP-users] RFNoC dataGenerator block not outputting to radio

OK, I have a weird problem.  I have a block I wrote a couple of months ago that doesn't seem to be working anymore.  I don't think I've updated anything within uhd-fpga except for some patches that Jonathon sent me so that I could add the logic in that keeps blocks from blasting data before the

[USRP-users] problem with aplay on E3xx

Just want to use a flowgraph that was working fine on an older (load-wise) SG1 E310 system on an up-to-date SG3 E312 system and it throws up if I were to type: aplay -i to start up the app, I get: root@ettus-e3xx-sg3:~# aplay -i ALSA lib /home/balister/docker-work/jethro/jethro-test/build/

[USRP-users] feedback from a USRP message

Is there anyway to get feedback from a sent message command to a USRP source in GR?  I was sending some commands and was /pretty/ sure I was doing it right, but to know for sure I sent a bogus command, and it didn't complain (I expected to see something on the terminal).  Is there anyway to tur

Re: [USRP-users] feedback from a USRP message

usrp source0 - Processing command message ((chan . 0) (badData . 24)) Am I giving too much credit to how the USRP error checks messages? On 10/30/2017 11:30 AM, Derek Kozel wrote: Hi Jason, The command message handling in the USRP source in GNU Radio is a bit interesting. The

Re: [USRP-users] Error when burn fpga image file into USRP X310

Did this ever get resolved?  Because I am having the same issues now too. Hi Luis, I will follow up with you on this issue off the list, within the thread that has been sent to support at ettus.com.

[USRP-users] Unable to load a custom FPGA image to USRP E312

s that correct? And is there something I can do in the bitstream generation process to prevent errors like this in the future? Thanks, Jason ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

[USRP-users] RFNoC OFDM Example - Timeout on Chan 0

is likely because the Sync block is not detecting a preamble - are there any changes I need to make to the example design so that the Sync block will detect the preamble correctly? Thanks, Jason Meyer ___ USRP-users mailing list USRP-users@lists.ettus.com

[USRP-users] (no subject)

I have been fighting for a day with issues on my N200s and N210s to no avail. These were working units, but are giving me the following: $ uhd_usrp_probe  [INFO] [UHD] linux; GNU C++ version 4.8.5 20150623 (Red Hat 4.8.5-16); Boost_105300; UHD_3.11.0.0-34-g4844f66d [ERROR] [UHD] Exception caught in

[USRP-users] bug in UHD I think

We have a python script that worked before I pulled down the latest UHD. A uhd_usrp_probe works fine, but when we run our command in our script using: usrp.get_usrp_info().vals()[0] We get an error of: LookupError: Path not found in tree: /mboards/0/xbar/Radio_0/eeprom partway through the Et

Re: [USRP-users] rfnoc build standard image x310 failing

I believe he means the UHD-3.15.LTS *branch*, not tag. See here: https://github.com/EttusResearch/uhd/tree/UHD-3.15.LTS Jason On 5/21/20 11:34 AM, Hodges, Jeff via USRP-users wrote: I apologize for my ignorance, which of these is the LTS tag? git tag -l 003_007_002_rc1 003_007_003_rc1

Re: [USRP-users] B200mini with GNSS-SDR

Those are probably jumps due to instantaneous changes in the frequency control in the internal TCXO. Try injecting an external 10 MHz reference clock and using that instead to see if it makes the jumps go away. Jason On 7/23/20 8:31 AM, Don Kelly via USRP-users wrote: Any other usrp-users

[USRP-users] N320 inverted spectrum when tuned below 450 MHz

ot tone is on the left, where they belong. Is this a known issue? Thank you. Jason ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Re: [USRP-users] N320 inverted spectrum when tuned below 450 MHz

On 10/14/20 2:41 PM, Marcus D. Leech via USRP-users wrote: On 10/14/2020 01:28 PM, Jason Roehm via USRP-users wrote: I have an N320 that I'm trying out for the first time. I'm using UHD 4.0.0, and I loaded the corresponding root filesystem data for that release to the N320. I find

[USRP-users] rfnoc debug block

Is there anything special to get the rfnoc debug block to work? I copied-and-pasted the section of rfnoc_debug.grc that seems to be relevant into my flowgraph. But when I try to run my flowgraph, I get: Traceback (most recent call last): File "/opt/gnuradio/v3.7.12.0_rfnoc/src/Channelizer/g

[USRP-users] RFNoC FPGA clear_tx_seqnum behavior

I know this is an older thread, but I too am struggling to bring a block that someone else designed for us in 2015.4 to work in 2017.4. I dug around but I don't see any of our custom blocks using clear_tx_seqnum in their sub-modules or their config registers. They do use the config registers qu

Re: [USRP-users] RFNoC FPGA clear_tx_seqnum behavior

ssage - Subject: Re: [USRP-users] RFNoC FPGA clear_tx_seqnum behavior From: "Brian Padalino" Date: 6/28/18 3:35 pm Cc: "USRP-users@lists.ettus.com" Hey Jason, On Thu, Jun 28, 2018 at 3:31 PM Jason Matusiak via USRP-users wrote: I know this is an older thread, b

Re: [USRP-users] RFNoC FPGA clear_tx_seqnum behavior

Thanks Brian, that seemed to be the trick, at least for the initial flowgraph I was trying to use (I think I must have missed a block in my second flowgraph). Sadly, I can only run it once and then it doesn't work on the second run, so I need to investigate that next. I feel like I remember so

Re: [USRP-users] RFNoC FPGA clear_tx_seqnum behavior

), .pkt_rst(bus_rst), + .samp_clk(ce_clk), .samp_rst(ce_rst | clear_tx_seqnum[i]), .pkt_clk(bus_clk), .pkt_rst(bus_rst | clear_tx_seqnum_bclk[i]), ~Jason - Original Message - Subject: RE: Re: Re: [USRP-users] RFNoC FPGA clear_tx_seqnum behavior Date: 7/2/18 6:54 am To:

[USRP-users] Problem with the most recent UHD changes building

I just tried to pull down and build a fresh RFNoC install and it keeps failing. I think this is related to the commit 827adb from a couple of days ago. I say this because that commit showed a change to ad9361_ctrl.hpp, and my error when running "yes |pybombs - prefix init /opt/gnuradio/v3.

Re: [USRP-users] Problem with the most recent UHD changes building

Hey Jon. Is it commit e4b4309? I'll give it a shot tomorrow. Thanks Original message From: Jon Pendlum Date: 7/4/18 8:47 PM (GMT-05:00)Cc: "USRP-users@lists.ettus.com" Subject: Re: [USRP-users] Problem with the most recent UHD changes building Hey Jas

Re: [USRP-users] Problem with the most recent UHD changes building

4309? I'll give it a shot tomorrow. Thanks Hey Jon. Is it commit e4b4309? I'll give it a shot tomorrow. Thanks Original message From: Jon Pendlum Date: 7/4/18 8:47 PM (GMT-05:00) Cc: "USRP-users@lists.ettus.com" Subject: Re: [USRP-users] Problem with the most

[USRP-users] noc_block_null_source_sink module

I was having trouble finding information on this block. I could see its usefulness in an application I am looking into, but I wasn't sure how complete the block was (I don't really see anything using it, nor a GRC xml file for it). Thanks ___ USRP-use

[USRP-users] RFNoC DMA FIFO

I have a silly question. How do I add the axi_dma_fifo to my build? It looks like we can't add it to the uhd_image_builder command line, so I am not sure the way to do it manually. Is this written up somewhere that I missed? ___ USRP-users mailing li

Re: [USRP-users] rfnoc debug block

I was wondering if anyone had thoughts on this? I am now seeing it on a brand new block that I tried to create today. A uhd_usrp_probe looks fine, but when I run the python generated by GRC, I am seeing the same error: Traceback (most recent call last): File "/home/jmat/rfnoc-nocblocks/example

[USRP-users] X310 software reset revisted

I know it has been questioned many times on here, but I wanted to verify something. It has always been said that there is no way to do a software reset on the X310; I am curious if that is "currently" or "ever?" I wasn't sure if there was a way to send a packet either via UHD or RFNoC that c

[USRP-users] RFNoC flowgraph runs right the second time

I have a flowgraph with a custom RFNoC block in the middle. That block has 2 inputs and 2 outputs. Just to get started and work out the MIMO functionality, all I do is cross the the inputs to the outputs (so input 0 comes out output 1). What I am seeing is that if I run the flowgraph after lo

[USRP-users] Any tips to speed up X310 Vivado build time?

I know Vivado build times are dependent on how optimized you want things and how utilized the FPGA is, but is there a way to speed up the build times? I started doing my builds on a server thinking it would be a huge boost from my PC, but I am not really seeing a difference. It has 64 cores an

Re: [USRP-users] RFNoC flowgraph runs right the second time

usage. > Jason, > > this is a tough one. I have no ideas, other than 'throw in a couple of > ILAs and see where it's stuck'. > -- M ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Re: [USRP-users] Creating Double Ported Source Block and Running It's Testbench

) *1-in 2-out (ditto to above's comment) *2-in 2-out sharing the stream *2-in 2-out using different paths for the two streams ~Jason - Original Message - Subject: [USRP-users] Creating Double Ported Source Block and Running It's Testbench From: "shachar J. brown

Re: [USRP-users] USRP X310 Remote Configuration

I've actually done this with success, unfortunately, I am not allowed to share it :(. It wasn't too hard, I used a core in the block to hold the data, and then I just repeated it when I sent it out over and over. The catch was that there was a little bit of an issue within rfnoc at the time (

[USRP-users] Possible to enable via RFNoC block via RFNoC

I am curious if it is possible to enable an RFNoC block from another RFNoC block? An example would be, turning on the siggen when another RFNoC block decides that it should run. I don't believe that I've seen this done anywhere, so I have a suspicion that there isn't a good way to get message

Re: [USRP-users] noc_block_null_source_sink module

like it is now), but connected a null sink to the unneeded output. Any words of wisdom? - Original Message - Subject: Re: [USRP-users] noc_block_null_source_sink module From: "Jon Pendlum" Date: 7/30/18 10:49 pm To: "Jason Matusiak" Cc: "Ettus Mail

[USRP-users] what would be considered an RFNoC loopback?

I am still having trouble with my OOT block when I add a second radio in the loop. A reminder of what I am doing. Just to test my 2-in, 2-out RFNoC block, I am swapping the inputs to the outputs (so input 0 goes to output 1). When I have: Radio->DDC->MyBlockIn.0 --- MyBlockOut.1->vecToStream

[USRP-users] Problem running RFNoC testbench all of a sudden

I am not sure what I've done, but all of a sudden I don't seem to be able to run my testbench. Things are in the "compiling" stage of the testbench when I get hit with this: Built simulation snapshot ddc_chain_behav ** Webtalk v2017.4 (64-bit) SW Build 2086221 on Fri Dec 15 20:5

Re: [USRP-users] Debugging RFNoC siggen

I experianced the same issues that EJ mentioned last year (maybe earlier). At the time Jon, helped me with a patch to get it to work properly (this was an OOT that sent out a specific chunk of samples on repeat [I think I mentioned this in a thread a few weeks ago]). I am not sure if it is fix

[USRP-users] packet size for RFNOC testbenches

I have been trying to figure out an issue with my block for a while, and it dawned on me that I might be barking up the wrong tree. I would like to send a lot of data for my test (say 5000+ samples). I noticed that things seem to get hosed after 496 samples. It might be an issue with my blo

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