I found the problem with my one flowgraph that was still not working after I
updated my blocks, it was the RFNoC "Split Stream" block. It appears that it
was never updated to use these new changes. I sort of modified it based on the
addsub block and it seems to work for me, but YMMV.
My changed were:
- wire [1:0] clear_tx_seqnum;
+ wire [1:0] clear_tx_seqnum, clear_tx_seqnum_bclk;
+synchronizer #(.INITIAL_VAL(1'b0), .WIDTH(2)) clear_tx_sync_i (
+ .clk(bus_clk), .rst(1'b0), .in(clear_tx_seqnum), .out(clear_tx_seqnum_bclk));
chdr_deframer_2clk chdr_deframer (
- .samp_clk(ce_clk), .samp_rst(ce_rst), .pkt_clk(bus_clk), .pkt_rst(bus_rst),
+ .samp_clk(ce_clk), .samp_rst(ce_rst), .pkt_clk(bus_clk), .pkt_rst(bus_rst |
clear_tx_seqnum_bclk),
chdr_framer_2clk #(.SIZE(MTU)) chdr_framer (
- .samp_clk(ce_clk), .samp_rst(ce_rst | clear_tx_seqnum[i]), .pkt_clk(bus_clk),
.pkt_rst(bus_rst),
+ .samp_clk(ce_clk), .samp_rst(ce_rst | clear_tx_seqnum[i]), .pkt_clk(bus_clk),
.pkt_rst(bus_rst | clear_tx_seqnum_bclk[i]),
~Jason
--------- Original Message --------- Subject: RE: Re: Re: [USRP-users] RFNoC
FPGA clear_tx_seqnum behavior
Date: 7/2/18 6:54 am
To: "Brian Padalino" <bpadal...@gmail.com>
Cc: "USRP-users@lists.ettus.com" <usrp-users@lists.ettus.com>
Thanks Brian, that seemed to be the trick, at least for the initial flowgraph
I was trying to use (I think I must have missed a block in my second flowgraph).
Sadly, I can only run it once and then it doesn't work on the second run, so I
need to investigate that next. I feel like I remember something in the mailing
list that was similar to that, so I will need to run that down (I am guessing
it has something to do with that clear_tx change again).
Thanks again, I owe you!
Now, if you're working off the latest rfnoc-devel as of today, I believe all
you need to do to port from a 2015.4 to 2017.4 design is:
- add bus_clk and bus_rst to the axi_wrapper instantiation if you use it
- use the chdr_framer_2clk/chdr_deframer_2clk versions instead since CHDR
operations changed clock domains
If you can't run uhd_usrp_probe and see your block listed after just adding the
bus_clk/bus_rst to axi_wrapper, then something else beyond what I've had to
debug is probably happening.
Hope this helps.
Brian
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