I believe he means the UHD-3.15.LTS *branch*, not tag. See here:
https://github.com/EttusResearch/uhd/tree/UHD-3.15.LTS
Jason
On 5/21/20 11:34 AM, Hodges, Jeff via USRP-users wrote:
I apologize for my ignorance, which of these is the LTS tag?
git tag -l
003_007_002_rc1
003_007_003_rc1
003_008_000_rc1
003_008_002_rc1
003_008_003_rc1
003_008_004_rc1
003_008_005_rc1
003_009_000_rc1
003_009_002_rc1
003_009_003_rc1
003_009_004_rc1
003_009_005_rc1
003_009_006_rc1
003_009_007_rc1
003_010_001_000_rc1
003_010_001_000_rc2
003_010_001_001_rc1
003_010_002_000_rc1
003_010_003_000_rc1
003_010_003_000_rc2
003_011_000_000_rc1
003_011_000_001_rc1
grcon_2016
n310_release-0.1
release_003_000_000
release_003_000_001
release_003_001_000
release_003_001_001
release_003_001_002
release_003_002_000
release_003_002_001
release_003_002_002
release_003_002_003
release_003_002_004
release_003_003_000
release_003_003_001
release_003_003_002
release_003_004_000
release_003_004_001
release_003_004_002
release_003_004_003
release_003_004_004
release_003_004_005
release_003_005_000
release_003_005_001
release_003_005_002
release_003_005_003
release_003_005_004
release_003_005_005
release_003_006_000
release_003_006_001
release_003_006_002
release_003_007_000
release_003_007_001
release_003_007_002
release_003_007_003
release_003_008_000
release_003_008_001
release_003_008_002
release_003_008_003
release_003_008_003-1
release_003_008_004
release_003_008_005
release_003_009_000
release_003_009_001
release_003_009_002
release_003_009_003
release_003_009_004
release_003_009_005
release_003_009_006
release_003_009_007
release_003_010_000_000
release_003_010_001_000
release_003_010_001_001
release_003_010_002_000
release_003_010_003_000
release_003_011_000_000
release_003_011_000_001
v3.11.0.0
v3.11.0.1
v3.11.0.1-20180419
v3.11.0.1-rc1
v3.11.1.0
v3.11.1.0-rc1
v3.12.0.0
v3.12.0.0-rc1
v3.12.0.1-rc1
v3.13.0.0
v3.13.0.0-rc1
v3.13.0.1
v3.13.0.2
v3.13.0.3-rc1
v3.13.1.0
v3.13.1.0-rc1
v3.13.1.0-rc2
v3.14.0.0
v3.14.0.0-a0-20181220
v3.14.0.0-a1-20181220
v3.14.0.0-rc1
v3.14.0.0-rc2
v3.14.0.0-rc3
v3.14.1.0
v3.14.1.0-rc1
v3.14.1.1
v3.14.1.1-rc1
v3.14.1.1.L
v3.15.0.0
v3.15.0.0-e310_prerelease
v3.15.0.0-rc2
v3.15.0.0-rc3
Jeff
*From:*Carmichael, Ryan <ryan.carmich...@dynetics.com>
*Sent:* Thursday, May 21, 2020 11:29 AM
*To:* usrp-users@lists.ettus.com
*Cc:* Hodges, Jeff <jeff.hod...@gtri.gatech.edu>
*Subject:* Re: [USRP-users] rfnoc build standard image x310 failing
I think you want to be using the UHD-3.15.LTS tag.
-Ryan
*From:*USRP-users <usrp-users-boun...@lists.ettus.com
<mailto:usrp-users-boun...@lists.ettus.com>> *On Behalf Of *Hodges,
Jeff via USRP-users
*Sent:* Thursday, May 21, 2020 10:25 AM
*To:* Jonathon Pendlum <jonathon.pend...@ettus.com
<mailto:jonathon.pend...@ettus.com>>
*Cc:* usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>;
Prado, Ron <ron.pr...@gtri.gatech.edu <mailto:ron.pr...@gtri.gatech.edu>>
*Subject:* [EXTERNAL] Re: [USRP-users] rfnoc build standard image x310
failing
Maybe there is a mistake in they way I am pulling the repository?
V3.14 with 2017.4 vivado failed:
cd ~/rfnoc/src
$ git clone --recursive https://github.com/EttusResearch/uhd
$ cd uhd
$ git checkout v3.14.1.1
$ git submodule update --init --recursive
V3.15 with 2018.3 vivado failed:
cd ~/rfnoc/src
$ git clone --recursivehttps://github.com/EttusResearch/uhd
$ cd uhd
$ git checkout v3.15.0.0
$ git submodule update --init --recursive
Am I pulling the wrong branches?
Looking at uhd_image_builder.py in v3.15.0.0:
44 wire ce_clk = radio_clk;
45 wire ce_rst = radio_rst;
Jeff
*From:*Jonathon Pendlum <jonathon.pend...@ettus.com
<mailto:jonathon.pend...@ettus.com>>
*Sent:* Thursday, May 21, 2020 2:01 AM
*To:* Hodges, Jeff <jeff.hod...@gtri.gatech.edu
<mailto:jeff.hod...@gtri.gatech.edu>>
*Cc:* usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>;
Prado, Ron <ron.pr...@gtri.gatech.edu <mailto:ron.pr...@gtri.gatech.edu>>
*Subject:* Re: [USRP-users] rfnoc build standard image x310 failing
Hi Jeff,
For UHD 3.15, I believe that issue has been fixed. Check out the
UHD-3.15.LTS branch and let me know if you still have an issue building.
For UHD 3.14, check out the UHD-3.14 branch.
Using the branches above, I was able to successfully build an image
using your uhd_image_builder command (without the -g option) for both
UHD 3.15 and UHD 3.14.
Jonathon
On Wed, May 20, 2020 at 8:35 PM Hodges, Jeff via USRP-users
<usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>> wrote:
Can someone please tell me what version of uhd and rfnoc are
compatible for building an image on Ubuntu 18.04?
I cannot get any of the UHD releases to properly build a standard
rfnoc image.
sudo ./uhd_image_builder.py fft ddc duc -g -t X310_RFNOC_HG -c -d
X310 --fill-with-fifos
I installed vivado 2018.3 with uhd 3.15.0.0 and get the error:
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net
bus_clk_gen/inst/CLK_OUT4 has multiple drivers:
radio_clk_gen/inst/clkout1_buf/O, and bus_clk_gen/inst/clkout4_buf/O.
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net
radio_reset_sync/reset_double_sync/synchronizer_false_path/value[9]_9
has multiple drivers:
radio_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q,
and
ce_reset_sync/reset_double_sync/synchronizer_false_path/stages[9].value_reg[9][0]/Q.
I installed vivado 2017.4 with uhd 3.14.1.1 and get this error:
BUILDER: Releasing IP location:
/home/nvd/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/aurora_64b66b_pcs_pma
Using parser configuration from:
/home/nvd/rfnoc/src/uhd/fpga-src/usrp3/top/x300/dev_config.json
[00:00:00] Executing command: vivado -mode batch -source
/home/nvd/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build_x300.tcl
-log build.log -journal x300.jou
CRITICAL WARNING: [filemgmt 20-1440] File
'/home/nvd/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit/user_design/rtl/clocking/mig_7series_v4_0_tempmon.v'
already exists in the project as a part of sub-design file
'/home/nvd/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit.xci'.
Explicitly adding the file outside the scope of the sub-design can
lead to unintended behaviors and is not recommended.
[00:00:29] Current task: Initialization +++ Current Phase: Starting
[00:00:29] Current task: Initialization +++ Current Phase: Finished
[00:00:29] Executing Tcl: synth_design -top x300 -part
xc7k410tffg900-2 -verilog_define BUILD_1G=1 -verilog_define
BUILD_10G=1 -verilog_define SFP0_1GBE=1 -verilog_define
SFP1_10GBE=1 -verilog_define RFNOC=1 -verilog_define X310=1
-verilog_define GIT_HASH=32'hfbb85bdf
[00:00:29] Starting Synthesis Command
ERROR: [Synth 8-439] module 'ddr3_32bit' not found
[/home/nvd/rfnoc/src/uhd/fpga-src/usrp3/top/x300/x300.v:1191]
ERROR: [Synth 8-285] failed synthesizing module 'x300'
[/home/nvd/rfnoc/src/uhd/fpga-src/usrp3/top/x300/x300.v:20]
ERROR: [Common 17-69] Command failed: Synthesis failed - please
see the console or run log file for details
[00:08:36] Current task: Synthesis +++ Current Phase: Starting
[00:08:36] Current task: Synthesis +++ Current Phase: Finished
[00:08:36] Process terminated. Status: Failure
Any advice is greatly appreciated.
Thanks,
Jeff
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