Re: [PATCH v3 068/162] tcg: Merge INDEX_op_muls2_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 17 + tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c| 6 ++ docs/d

Re: [PATCH v3 070/162] tcg: Merge INDEX_op_mulu2_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 17 + tcg/tcg-op.c | 10 +- tcg/tcg.c| 9 +++-- tcg/tci.c| 6 ++ docs

Re: [PULL 11/17] gdbstub: Try unlinking the unix socket before binding

Hi Alex and Paolo, I hit an compiling error with "./configure --enable-rust" at this patch: [69/124] Compiling Rust source ../rust/qemu-api/tests/tests.rs FAILED: rust/qemu-api/rust-qemu-api-integration rustc -C linker=cc -C link-arg=-m64 --color=auto -C debug-assertions=yes -C overflow-checks=n

Re: [PATCH v3] qemu/compiler: Absorb 'clang-tsa.h'

On 17/1/25 18:02, Philippe Mathieu-Daudé wrote: We already have "qemu/compiler.h" for compiler-specific arrangements, automatically included by "qemu/osdep.h" for each source file. No need to explicitly include a header for a Clang particularity. Suggested-by: Pierrick Bouvier Reviewed-by: Pier

Re: [PATCH v3 102/162] tcg: Merge INDEX_op_deposit_{i32,i64}

On 17/2/25 00:09, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 2 +- tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c| 6 ++ docs/devel/tcg-ops.rst |

Re: [PATCH v3 095/162] tcg: Merge INDEX_op_sextract_{i32,i64}

On 17/2/25 00:09, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 22 +++--- tcg/tcg-op.c | 12 ++-- tcg/tcg.c| 9 +++-- tcg/tci.c| 12 --

Re: [PATCH v3 104/162] tcg: Merge INDEX_op_extract2_{i32,i64}

On 17/2/25 00:09, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 5 + tcg/optimize.c | 10 +- tcg/tcg-op.c | 16 tcg/tcg.c | 6 ++ docs/devel/tcg-ops.rst | 4 ++--

[PATCH 6/8] target/riscv/kvm: add CSR_SIREG and CSR_STOPEI emulation

Support user-space emulation of SIREG and STOPEI CSR with KVM acceleration. For SIREG emulation, the SISELECT CSR value and iprio array must be loaded before handling, and since the iprio array might be modified, it must be written back after the emulation. When running with KVM acceleration, the

[PATCH v2 2/6] memory: Change memory_region_set_ram_discard_manager() to return the result

Modify memory_region_set_ram_discard_manager() to return false if a RamDiscardManager is already set in the MemoryRegion. The caller must handle this failure, such as having virtio-mem undo its actions and fail the realize() process. Opportunistically move the call earlier to avoid complex error ha

[PATCH v2 3/6] memory-attribute-manager: Introduce MemoryAttributeManager to manage RAMBLock with guest_memfd

As the commit 852f0048f3 ("RAMBlock: make guest_memfd require uncoordinated discard") highlighted, some subsystems like VFIO may disable ram block discard. However, guest_memfd relies on the discard operation to perform page conversion between private and shared memory. This can lead to stale IOMMU

[PATCH 8/8] docs: update the description about RISC-V AIA

Add the description about "-accel kvm,kernel-irqchip=off" into docs/specs/riscv-aia.rst and docs/system/riscv/virt.rst. Signed-off-by: Yong-Xuan Wang --- docs/specs/riscv-aia.rst | 24 ++-- docs/system/riscv/virt.rst | 10 ++ 2 files changed, 24 insertions(+), 10 de

[PATCH v2 6/6] RAMBlock: Make guest_memfd require coordinate discard

As guest_memfd is now managed by memory_attribute_manager with RamDiscardManager, only block uncoordinated discard. Signed-off-by: Chenyi Qiang --- Changes in v2: - Change the ram_block_discard_require(false) to ram_block_coordinated_discard_require(false). --- system/physmem.c | 6 +++

[PATCH 3/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_SMSTATEEN

Add KVM_REG_RISCV_CSR_SMSTATEEN support to get/set the context of Smstateen extension in VS mode. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c in

[PATCH 1/4] hw/riscv/virt: KVM AIA refinement

KVM AIA is only needed to be set when the virt machine use the AIA MSI. So we can move the KVM AIA configuration into virt_create_aia() to reduce the condition checking. Signed-off-by: Yong-Xuan Wang --- hw/riscv/virt.c | 79 +++-- 1 file changed, 37 i

[PATCH 0/8] riscv: AIA: kernel-irqchip=off support

This series introduces the user-space AIA MSI emulation when using KVM acceleration. After this series, RISC-V QEMU virt machine with KVM acceleration has 3 parameters to control the type of irqchip and its emulation method: - Machine prop "aia" controls the type of irqchip - none: use PLIC and

[PATCH 1/8] target/riscv/kvm: rewrite get/set for KVM_REG_RISCV_CSR

As KVM_REG_RISCV_CSR includes several subtypes of CSR, rewrite the related macros and functions to prepare for other subtypes. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 70 +++--- 1 file changed, 43 insertions(+), 27 deletions(-) diff --git a

[PATCH 5/8] target/riscv/kvm: rewrite kvm_riscv_handle_csr

Rewrite the kvm_riscv_handle_csr() to support additional CSR emulation in user space with KVM acceleration. This update reuses the TCG CSR emulation function to simplify the implementation and reduce the redundant work. Also it introduces two hook functions for certain CSRs. Before emulation, the r

Re: [PATCH v3 062/162] tcg: Merge INDEX_op_clz_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 10 +- tcg/tcg-op.c | 22 ++ tcg/tcg.c| 6 ++ tcg/tci.c| 4 ++-- docs

Re: [PATCH v2] hpet: do not overwrite properties on post_load

Il lun 17 feb 2025, 07:35 Zhao Liu ha scritto: > > @@ -347,14 +330,13 @@ static const VMStateDescription vmstate_hpet = { > > .version_id = 2, > > .minimum_version_id = 1, > > .pre_save = hpet_pre_save, > > -.pre_load = hpet_pre_load, > > .post_load = hpet_post_load, > >

Re: [PATCH v3 066/162] tcg: Merge INDEX_op_ctpop_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 9 +++-- tcg/tcg-op.c | 21 ++--- tcg/tcg.c| 6 ++ tcg/tci.c| 6 ++ docs

[PATCH v4] net: vhost-user: add QAPI events to report connection state

The netdev reports NETDEV_VHOST_USER_CONNECTED event when the chardev is connected, and NETDEV_VHOST_USER_DISCONNECTED when it is disconnected. The NETDEV_VHOST_USER_CONNECTED event includes the chardev id. This allows a system manager like libvirt to detect when the server fails. For instance w

[PULL 3/4] tests/qtest/ufs-test: Prepare for MCQ test

In legacy doorbell mode, the command descriptor slot matched the UTRD slot. To maintain consistency in MCQ mode, command descriptor slot allocation and deallocation now use a bitmap-based approach. Acked-by: Fabiano Rosas Signed-off-by: Jeuk Kim --- tests/qtest/ufs-test.c | 562

[PULL 2/4] tests/qtest/ufs-test: Cleanup unused code

Removed dead code related to the unimplemented task management request. Acked-by: Fabiano Rosas Signed-off-by: Jeuk Kim --- tests/qtest/ufs-test.c | 11 +-- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/tests/qtest/ufs-test.c b/tests/qtest/ufs-test.c index 1f860b41c0..ce

[PULL 0/4] ufs queue

s/pull-ufs-20250217 for you to fetch changes up to a54596a96006096798b172a368ae952a231f9f72: tests/qtest/ufs-test: Add test code for MCQ functionality (2025-02-17 18:20:53 +0900) ufs updates for MCQ testing - Remove u

Re: CXL CCI Get/Set Alert Configuration commands implmented as per CXL Specification 3.2 section 8.2.10.9.3

On 14/02/25 05:43PM, Jonathan Cameron wrote: On Fri, 14 Feb 2025 18:52:11 +0530 Sweta Kumari wrote: 1)get alert configuration(Opcode 4201h) 2)set alert configuration(Opcode 4202h) Move the change log to below the --- The key thing being git then doesn't pick it up whilst applying the patch.

Re: [PULL 23/27] i386: enable rust hpet for pc when rust is enabled

Hi Paolo, > --- a/hw/timer/Kconfig > +++ b/hw/timer/Kconfig > @@ -11,7 +11,7 @@ config A9_GTIMER > > config HPET > bool > -default y if PC > +default y if PC && !HAVE_RUST + +config X_HPET_RUST +bool +default y if PC && HAVE_RUST > config I8254 > bool This patch do

[PATCH] ui/sdl: only compile dmabuf support if CONFIG_GBM

From: Marc-André Lureau Fix SDL backend compilation for win32. Fixes: commit 31287d1af4 ("ui/sdl2: Implement dpy dmabuf functions") Signed-off-by: Marc-André Lureau --- ui/sdl2-gl.c | 2 ++ ui/sdl2.c| 4 2 files changed, 6 insertions(+) diff --git a/ui/sdl2-gl.c b/ui/sdl2-gl.c index

[PATCH] docs/cxl: Add serial number for persistent-memdev

Add serial number parameter in the cxl persistent examples. Signed-off-by: Yuquan Wang --- docs/system/devices/cxl.rst | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index 882b036f5e..e307caf3f8 100

Re: [PATCH v3 078/162] tcg: Merge INDEX_op_brcond_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 4 +--- tcg/optimize.c | 6 +++--- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 24 tcg/tci.c| 6 ++ docs/

Re: [PATCH v3 080/162] tcg: Merge INDEX_op_movcond_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 2 +- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 15 +-- tcg/tci.c| 4 ++-- docs/devel/tcg-ops.rs

Re: [PATCH v3 087/162] tcg: Merge INDEX_op_bswap16_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 7 +++ tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c| 5 ++--- docs/devel/tcg-ops.rst

Re: [PATCH v3 089/162] tcg: Merge INDEX_op_bswap32_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 4 +--- tcg/optimize.c | 7 +++ tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c| 5 ++--- docs/devel/tcg-o

Re: [PATCH v3 064/162] tcg: Merge INDEX_op_ctz_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 10 +- tcg/tcg-op.c | 16 tcg/tcg.c| 6 ++ tcg/tci.c| 4 ++-- docs/devel

Re: [PATCH v3 093/162] tcg: Merge INDEX_op_extract_{i32,i64}

On 17/2/25 00:09, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 14 -- tcg/tcg-op.c | 8 tcg/tcg.c| 9 +++-- tcg/tci.c| 12 doc

RE: [RFC PATCH 0/5] hw/arm/virt: Add support for user-creatable nested SMMUv3

Hi Shameer, Nicolin, >-Original Message- >From: Duan, Zhenzhong >Subject: RE: [RFC PATCH 0/5] hw/arm/virt: Add support for user-creatable nested >SMMUv3 > >Hi Shameer, > >>-Original Message- >>From: Shameerali Kolothum Thodi >>Subject: RE: [RFC PATCH 0/5] hw/arm/virt: Add support

Re: [PATCH 3/5] target/rx: Reset the CPU at qemu reset time

On Sat, 15 Feb 2025 at 02:17, Keith Packard via wrote: > > This ensure that the CPU gets reset every time QEMU resets. > > Signed-off-by: Keith Packard > --- > target/rx/cpu.c | 11 ++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/target/rx/cpu.c b/target/rx/cpu.c >

Re: [PATCH] stub: Remove monitor-fd.c

On Mon, Feb 17, 2025 at 11:48:49AM +0100, Ilya Leoshkevich wrote: > Date: Mon, 17 Feb 2025 11:48:49 +0100 > From: Ilya Leoshkevich > Subject: [PATCH] stub: Remove monitor-fd.c > X-Mailer: git-send-email 2.48.1 > > Both monitor-fd.c and monitor-internal.c contain a stub for > monitor_get_fd(), whi

Re: [PATCH 28/42] qapi/parser: prohibit untagged sections between tagged sections

John Snow writes: > This is being done primarily to ensure consistency between the source > documents and the final, rendered HTML output. Because > member/feature/returns sections will always appear in a visually grouped > element in the HTML output, prohibiting free paragraphs between those > s

Re: [PATCH] ui/sdl: only compile dmabuf support if CONFIG_GBM

Hi On Mon, Feb 17, 2025 at 3:16 PM wrote: > > From: Marc-André Lureau > > Fix SDL backend compilation for win32. > > Fixes: commit 31287d1af4 ("ui/sdl2: Implement dpy dmabuf functions") Pierre-Eric, I realize this is not yet upstream. Can you update your patch? thanks > > Signed-off-by: Marc-

[PATCH 4/8] target/riscv: add helper to get CSR name

Add a helper function to get CSR name from CSR number. Signed-off-by: Yong-Xuan Wang --- target/riscv/cpu.h | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 616c3bdc1c24..133d1852ee1e 100644 --- a/target/riscv/cpu.h +++ b/targ

[PATCH v2 1/6] memory: Export a helper to get intersection of a MemoryRegionSection with a given range

Rename the helper to memory_region_section_intersect_range() to make it more generic. Meanwhile, define the @end as Int128 and replace the related operations with Int128_* format since the helper is exported as a wider API. Suggested-by: Alexey Kardashevskiy Reviewed-by: David Hildenbrand Signed

[PATCH 4/4] hw/intc/aplic: refine kvm_msicfgaddr

Let kvm_msicfgaddr use the same format with mmsicfgaddr and smsicfgaddr. Signed-off-by: Yong-Xuan Wang --- hw/intc/riscv_aplic.c | 24 +--- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index e5714267c096..5964cd

[PATCH v2 5/6] memory: Attach MemoryAttributeManager to guest_memfd-backed RAMBlocks

Introduce a new field, memory_attribute_manager, in RAMBlock to link to an MemoryAttributeManager object. This change centralizes all guest_memfd state information (like fd and shared_bitmap) within a RAMBlock, making it easier to manage. Use the realize()/unrealize() helpers to initialize/uniniti

[PATCH 2/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_AIA

Add KVM_REG_RISCV_CSR_AIA support to get/set the context of AIA extension in VS mode. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 45 ++ 1 file changed, 45 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c i

[PATCH 3/4] hw/intc/aplic: refine the APLIC realize

When the APLIC is emulated in the kernel, the GPIO output lines to CPUs can be remove. In this case the APLIC trigger CPU interrupts by KVM APIs. This patch also move the code that claim the CPU interrupts to the beginning of APLIC realization. This can avoid the unnecessary resource allocation be

[PATCH 0/4] riscv: AIA: refinement for KVM acceleration

Reorder the code to reduce the conditional checking and remove unnecessary resource setting when using in-kernl AIA irqchip. Yong-Xuan Wang (4): hw/riscv/virt: KVM AIA refinement hw/intc/imsic: refine the IMSIC realize hw/intc/aplic: refine the APLIC realize hw/intc/aplic: refine kvm_msicf

[PATCH 2/4] hw/intc/imsic: refine the IMSIC realize

When the IMSIC is emulated in the kernel, the GPIO output lines to CPUs and aia_ireg_rmw_fn setting can be remove. In this case the IMSIC trigger CPU interrupts by KVM APIs, and the RMW of IREG is handled in kernel. This patch also move the code that claim the CPU interrupts to the beginning of IM

[PATCH v2 4/6] memory-attribute-manager: Introduce a callback to notify the shared/private state change

Introduce a new state_change() callback in MemoryAttributeManagerClass to efficiently notify all registered RamDiscardListeners, including VFIO listeners about the memory conversion events in guest_memfd. The existing VFIO listener can dynamically DMA map/unmap the shared pages based on conversion

[PATCH 7/8] target/riscv/kvm: rename riscv-aia to riscv-imsic

The riscv-aia property only controls the in-kernel IMSIC mode, the emulation of AIA MSI mode is controlled by the kernel-irqchip property. Rename the riscv-aia property to riscv-imsic to prevent the confusion. Signed-off-by: Yong-Xuan Wang --- target/riscv/kvm/kvm-cpu.c | 52

Re: [PATCH v2] hpet: do not overwrite properties on post_load

On Mon, Feb 17, 2025 at 09:02:24AM +0100, Paolo Bonzini wrote: > Date: Mon, 17 Feb 2025 09:02:24 +0100 > From: Paolo Bonzini > Subject: Re: [PATCH v2] hpet: do not overwrite properties on post_load > > Il lun 17 feb 2025, 07:35 Zhao Liu ha scritto: > > > > @@ -347,14 +330,13 @@ static const VMS

Re: [PATCH v3 154/162] tcg: Merge INDEX_op_ld*_{i32,i64}

On 17/2/25 00:10, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 19 +--- tcg/optimize.c | 27 - tcg/tcg-op.c | 24 +++ tcg/tcg.c| 64 ++--

Re: [PATCH v3 162/162] tcg: Remove tcg_out_op

On 17/2/25 00:10, Richard Henderson wrote: All integer opcodes are now converted to TCGOutOp. Signed-off-by: Richard Henderson --- tcg/tcg.c| 12 +++- tcg/aarch64/tcg-target.c.inc | 7 --- tcg/arm/tcg-target.c.inc | 7 --- tcg/i386/tcg-

Re: [PATCH v3 051/162] tcg: Merge INDEX_op_remu_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 5 + tcg/optimize.c | 9 + tcg/tcg-op.c | 8 tcg/tcg.c| 6 ++ tcg/tci.c| 4 ++-- docs/devel/tcg-ops.rst

Re: [PATCH v3 043/162] tcg: Merge INDEX_op_divu_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 9 + tcg/tcg-op.c | 16 tcg/tcg.c| 6 ++ tcg/tci.c| 5 ++--- docs/devel

Re: [PULL 00/22] Migration patches for 2025-02-14

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL 00/27] rust, Windows patches for 2025-02-13

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL 00/39] Misc HW patches for 2025-02-16

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

[PATCH v2 0/6] Enable shared device assignment

This is the v2 series of the shared device assignment support. The overview of this series: - Patch 1-2: preparation patches. One is to export a helper to get intersection of a MemoryRegionSection with a given range. The other is to change the memory_region_set_ram_discard_manager() to return

Re: [PATCH v3 053/162] tcg: Merge INDEX_op_shl_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 10 +- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 6 ++ tcg/tci.c| 13 - docs/devel/tc

Re: [PULL 00/24] tcg patch queue

Please take a look at the following CI failure: https://gitlab.com/qemu-project/qemu/-/jobs/9153630625#L5195 Thanks, Stefan

Re: [PULL 0/4] Trivial patches for 2025-02-14

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes. signature.asc Description: PGP signature

Re: [PATCH v3 057/162] tcg: Merge INDEX_op_sar_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 12 ++-- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 6 ++ tcg/tci.c| 12 docs/devel/t

Re: [PATCH v3 055/162] tcg: Merge INDEX_op_shr_{i32,i64}

On 17/2/25 00:08, Richard Henderson wrote: Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 17 +++-- tcg/tcg-op.c | 4 ++-- tcg/tcg.c| 6 ++ tcg/tci.c| 11 +++ docs/dev

Re: [PATCH] net: vhost-user: add QAPI events to report connection state

On 14/02/2025 15:19, Daniel P. Berrangé wrote: On Fri, Feb 14, 2025 at 01:59:20PM +, Daniel P. Berrangé wrote: On Fri, Feb 14, 2025 at 11:18:55AM +0100, Laurent Vivier wrote: On 14/02/2025 11:06, Markus Armbruster wrote: Laurent Vivier writes: The netdev reports NETDEV_VHOST_USER_CONNEC

[PATCH] stub: Remove monitor-fd.c

Both monitor-fd.c and monitor-internal.c contain a stub for monitor_get_fd(), which causes a duplicate symbol linker error when linking rust-qemu-api-integration. Use monitor-internal.c instead of monitor-fd.c and remove the latter. Reported-by: Zhao Liu Suggested-by: Zhao Liu Fixes: fccb744f41c

Re: [PATCH 29/42] qapi: Add "Details:" disambiguation marker

John Snow writes: > This clarifies sections that are mistaken by the parser as "intro" > sections to be "details" sections instead. > > Signed-off-by: John Snow Is this missing announce-self in net.json? diff --git a/qapi/net.json b/qapi/net.json index 49bc7de64e..44ed72dbe9 100644 --- a/qapi/

Re: [PATCH v4 26/33] vfio/migration: Multifd device state transfer support - receive init/cleanup

On 2/14/25 21:55, Maciej S. Szmigiero wrote: On 12.02.2025 11:55, Cédric Le Goater wrote: On 1/30/25 11:08, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" Add support for VFIOMultifd data structure that will contain most of the receive-side data together with its init/cleanup methods.

Re: [PATCH 4/5] target/rx: Load reset vector from memory after first run

On Sat, 15 Feb 2025 at 18:24, Richard Henderson wrote: > > On 2/14/25 18:16, Keith Packard via wrote: > > The ROM images all get deleted as they've been loaded to memory, so we > > can't go fetch the reset vector from there. Instead, fetch it from > > memory. To make that work, we need to execute

[PULL 4/4] tests/qtest/ufs-test: Add test code for MCQ functionality

This patch tests whether MCQ initialization and basic read-write operations work correctly when the MCQ parameter of hw/ufs is enabled. Acked-by: Fabiano Rosas Signed-off-by: Jeuk Kim --- tests/qtest/ufs-test.c | 171 ++--- 1 file changed, 142 insertions(+),

[PULL 1/4] hw/ufs: Fix legacy single doorbell support bit

QEMU UFS has supported both legacy single doorbell and MCQ, but the LSDBS value was incorrectly set. This change corrects the LSDBS value to 0. Signed-off-by: Jeuk Kim --- hw/ufs/ufs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ufs/ufs.c b/hw/ufs/ufs.c index 428fe927a

Re: [PATCH 29/42] qapi: Add "Details:" disambiguation marker

John Snow writes: > This clarifies sections that are mistaken by the parser as "intro" > sections to be "details" sections instead. > > Signed-off-by: John Snow > --- > qapi/machine.json | 2 ++ > qapi/migration.json| 4 > qapi/qom.json | 4 > qapi/yank.json

Re: [PATCH v7] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.

On Mon, Feb 17, 2025 at 5:25 AM Alistair Francis wrote: > > On Wed, Feb 12, 2025 at 8:20 PM Rajnesh Kanwal wrote: > > > > CTR entries are accessed using ctrsource, ctrtarget and ctrdata > > registers using smcsrind/sscsrind extension. This commits extends > > the csrind extension to support CTR r

Re: [PATCH 03/11] tcg/arm: Drop addrhi from prepare_host_addr

On 5/2/25 05:03, Richard Henderson wrote: The guest address will now always be TCG_TYPE_I32. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 63 ++-- 1 file changed, 21 insertions(+), 42 deletions(-) /* * Add the tl

Re: [PATCH 29/42] qapi: Add "Details:" disambiguation marker

John Snow writes: > This clarifies sections that are mistaken by the parser as "intro" > sections to be "details" sections instead. > > Signed-off-by: John Snow This is rather terse. Why does the boundary between "intro" (previously "body") and "details" matter? As far as I understand, it mat

Re: [PATCH] physmem: replace assertion with error

Hi Paolo, On 17/2/25 13:08, Paolo Bonzini wrote: It is possible to start QEMU with a confidential-guest-support object even in TCG mode. While there is already a check in qemu_machine_creation_done: if (machine->cgs && !machine->cgs->ready) { error_setg(errp, "accelerator does no

Re: [PATCH] physmem: replace assertion with error

On Mon, Feb 17, 2025 at 01:08:12PM +0100, Paolo Bonzini wrote: > It is possible to start QEMU with a confidential-guest-support object > even in TCG mode. While there is already a check in > qemu_machine_creation_done: > > if (machine->cgs && !machine->cgs->ready) { > error_setg(errp

Re: [PATCH v2 3/3] docs: Fix "Arm" capitalization

Hi, On 2/17/25 5:37 PM, Kashyap Chamarthy wrote: > This is based on Peter's suggestion here[1]. > > I simply addrressed the occurrences that I found with `git grep "ARM "` adressed > in the docs/ directory. I didn't touch stuff like these "StrongARM", > ARM926EJ-S, ARM1176JZS, etc. Related com

Re: [PATCH v2 1/3] docs/cpu-features: Consistently use vCPU instead of VCPU

On 2/17/25 5:37 PM, Kashyap Chamarthy wrote: > Signed-off-by: Kashyap Chamarthy Reviewed-by: Eric Auger Eric > --- > docs/system/arm/cpu-features.rst | 20 ++-- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/docs/system/arm/cpu-features.rst > b/docs/sy

Re: [PATCH v6 00/10] Support virtio-gpu DRM native context

On 2/17/25 18:22, Alex Bennée wrote: ... >> This VK_KHR_display problem is only reproducible with your rootfs that >> you shared with me. It could be a trouble with your build configs or a >> buggy package version used by your rootfs build, more likely the >> former. > So you have built that latest

Re: [PATCH V2 06/45] vfio/container: reform vfio_connect_container cleanup

On 2/14/25 15:13, Steve Sistare wrote: Replace the proliferation of exit labels in vfio_connect_container with conditionals for cleaning each piece of state. No functional change. Signed-off-by: Steve Sistare Reviewed-by: Cédric Le Goater Thanks, C. --- hw/vfio/container.c | 61

Re: [PATCH 20/21] hw/i2c: Import TCA6416 emulation from Xilinx

Am 3. Februar 2025 05:42:55 UTC schrieb Dmitriy Sharikhin : >At Sun, 02/02/2025 at 18:09 +0100, Philippe Mathieu-Daudé writes: >> No clue about compatibility. If you unfortunately need to add it, >> then please address my comments in the next version. >TCA6416 is _way_ more complex device than

Re: [PATCH 01/10] fpu: Make targets specify floatx80 default Inf at runtime

On 2/17/25 04:50, Peter Maydell wrote: Currently we hardcode at compile time whether the floatx80 default Infinity value has the explicit integer bit set or not (x86 sets it; m68k does not). To be able to compile softfloat once for all targets we'd like to move this setting to runtime. Define a

Re: [PATCH V2 07/45] vfio/container: vfio_container_group_add

On 2/14/25 15:13, Steve Sistare wrote: Add vfio_container_group_add to de-dup some code. No functional change. Signed-off-by: Steve Sistare Reviewed-by: Cédric Le Goater Thanks, C. --- hw/vfio/container.c | 47 +-- 1 file changed, 25 inse

[PATCH v4] vfio: Add property documentation

Investigate the git history to uncover when and why the VFIO properties were introduced and update the models. This is mostly targeting vfio-pci device, since vfio-platform, vfio-ap and vfio-ccw devices are simpler. Sort the properties based on the QEMU version in which they were introduced. Cc:

Re: [PATCH 04/10] fpu: Make targets specify whether floatx80 Inf can have Int bit clear

On 2/17/25 04:50, Peter Maydell wrote: In Intel terminology, a floatx80 Infinity with the explicit integer bit clear is a "pseudo-infinity"; for x86 these are not valid infinity values. m68k is looser and does not care whether the Integer bit is set or clear in an infinity. Move this setting to

Re: [PATCH 02/10] target/m68k: Avoid using floatx80_infinity global const

On 2/17/25 04:50, Peter Maydell wrote: The global const floatx80_infinity is (unlike all the other float*_infinity values) target-specific, because whether the explicit Integer bit is set or not varies between m68k and i386. We want to be able to compile softfloat once for multiple targets, so w

Re: [PULL 27/27] ui/sdl2: reenable the SDL2 Windows keyboard hook procedure

On Sat, Feb 15, 2025 at 6:36 PM Michael Tokarev wrote: > This looks like a qemu-stable material. Please let me know if it is not. Yes, that makes sense. Thanks Michael. Paolo

Re: [PATCH 16/20] cpus: Restrict cpu_common_post_load() code to TCG

On 26/1/25 22:16, Richard Henderson wrote: On 1/23/25 15:44, Philippe Mathieu-Daudé wrote: CPU_INTERRUPT_EXIT was removed in commit 3098dba01c7 ("Use a dedicated function to request exit from execution loop"), tlb_flush() and tb_flush() are related to TCG accelerator. Signed-off-by: Philippe Ma

Re: [PULL 23/27] i386: enable rust hpet for pc when rust is enabled

On 2/17/25 12:03, Zhao Liu wrote: Hi Paolo, --- a/hw/timer/Kconfig +++ b/hw/timer/Kconfig @@ -11,7 +11,7 @@ config A9_GTIMER config HPET bool -default y if PC +default y if PC && !HAVE_RUST + +config X_HPET_RUST +bool +default y if PC && HAVE_RUST config I8254

Re: [PATCH v2 00/28] x86: Improve operation under QEMU

Hi Tom, On Sun, 16 Feb 2025 at 14:57, Tom Rini wrote: > > On Sun, Feb 16, 2025 at 01:43:45PM -0700, Simon Glass wrote: > > > U-Boot can start and boot an OS in both qemu-x86 and qemu-x86_64 but it > > is not perfect. > > > > With both builds, executing the VESA ROM causes an intermittent hang, at

[PATCH 5/5] accel/tcg: Move cpu_memory_rw_debug() user implementation to user-exec.c

cpu_memory_rw_debug() system implementation is defined in system/physmem.c. Move the user one to accel/tcg/user-exec.c to simplify cpu-target.c maintenance. Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/user-exec.c | 80 ++ cpu-target.c | 90 +--

Re: [PATCH v3 091/162] tcg: Rename INDEX_op_bswap64_i64 to INDEX_op_bswap64

On 17/2/25 00:09, Richard Henderson wrote: Even though bswap64 can only be used with TCG_TYPE_I64, rename the opcode to maintain uniformity. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 3 +-- tcg/optimize.c | 6 +++--- tcg/tcg-op.c | 4 ++-- tcg/tc

Re: [PATCH 08/10] fpu: Always decide snan_bit_is_one() at runtime

On 17/2/25 13:50, Peter Maydell wrote: Currently we have a compile-time shortcut where we return a hardcode value from snan_bit_is_one() on everything except MIPS, because we know that's the only target that needs to change status->no_signaling_nans at runtime. Remove the ifdef, so we always loo

[PATCH] physmem: replace assertion with error

It is possible to start QEMU with a confidential-guest-support object even in TCG mode. While there is already a check in qemu_machine_creation_done: if (machine->cgs && !machine->cgs->ready) { error_setg(errp, "accelerator does not support confidential guest %s", o

Re: [PATCH 7/8] target/riscv/kvm: rename riscv-aia to riscv-imsic

On Mon, Feb 17, 2025 at 04:17:27PM +0800, Yong-Xuan Wang wrote: > The riscv-aia property only controls the in-kernel IMSIC mode, the > emulation of AIA MSI mode is controlled by the kernel-irqchip property. > Rename the riscv-aia property to riscv-imsic to prevent the confusion. > > Signed-off-by:

Re: [PATCH] meson: Display summary of Darwin libraries detected

On Wed, Feb 12, 2025 at 12:29:58PM +0100, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé > --- > meson.build | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/meson.build b/meson.build > index 18cf9e2913b..10f4c9fd30d 100644 > --- a/meson.build > +++ b/meson.

[PATCH 01/10] fpu: Make targets specify floatx80 default Inf at runtime

Currently we hardcode at compile time whether the floatx80 default Infinity value has the explicit integer bit set or not (x86 sets it; m68k does not). To be able to compile softfloat once for all targets we'd like to move this setting to runtime. Define a new FloatX80Behaviour enum which is a se

[PATCH 02/10] target/m68k: Avoid using floatx80_infinity global const

The global const floatx80_infinity is (unlike all the other float*_infinity values) target-specific, because whether the explicit Integer bit is set or not varies between m68k and i386. We want to be able to compile softfloat once for multiple targets, so we can't continue to use a single global w

[PATCH 06/10] fpu: Move m68k_denormal fmt flag into floatx80_behaviour

Currently we compile-time set an 'm68k_denormal' flag in the FloatFmt for floatx80 for m68k. This controls our handling of what the Intel documentation calls a "pseudo-denormal": a value where the exponent field is zero and the explicit integer bit is set. For x86, the x87 FPU is supposed to acce

[PATCH 09/10] fpu: Don't compile-time disable hardfloat for PPC targets

We happen to know that for the PPC target the FP status flags (and in particular float_flag_inexact) will always be cleared before a floating point operation, and so can_use_fpu() will always return false. So we speed things up a little by forcing QEMU_NO_HARDFLOAT to true on that target. We woul

  1   2   3   4   >