On Tue, 4 Feb 2025 at 09:21, Bernhard Beschow <shen...@gmail.com> wrote:
>
> On the real device, the PCIe root bus is only connected to a PCIe bridge and
> does not allow for direct attachment of devices. Doing so in QEMU results in
> no
> PCI devices being detected by Linux. Instead, PCI devices should plug into the
> secondary PCIe bus spawned by the internal PCIe bridge.
>
> Unfortunately, QEMU defaults to plugging devices into the PCIe root bus. To
> work
> around this, every PCI device created on the command line needs an extra
> `bus=dw-pcie` option which is error prone. Fix that by marking the PCIe root
> bus
> as full which makes QEMU decend into the child PCIe bus.
>
> Signed-off-by: Bernhard Beschow <shen...@gmail.com>
> ---
> include/hw/pci-host/designware.h | 7 +++++++
> hw/pci-host/designware.c | 18 +++++++++++++++++-
> 2 files changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/pci-host/designware.h
> b/include/hw/pci-host/designware.h
> index bf8b278978..a35a3bd06c 100644
> --- a/include/hw/pci-host/designware.h
> +++ b/include/hw/pci-host/designware.h
> @@ -25,12 +25,19 @@
> #include "hw/pci/pci_bridge.h"
> #include "qom/object.h"
>
> +#define TYPE_DESIGNWARE_PCIE_ROOT_BUS "designware-pcie-root-BUS"
> +OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIERootBus, DESIGNWARE_PCIE_ROOT_BUS)
> +
> #define TYPE_DESIGNWARE_PCIE_HOST "designware-pcie-host"
> OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIEHost, DESIGNWARE_PCIE_HOST)
>
> #define TYPE_DESIGNWARE_PCIE_ROOT "designware-pcie-root"
> OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIERoot, DESIGNWARE_PCIE_ROOT)
>
> +struct DesignwarePCIERootBus {
> + PCIBus parent;
> +};
> +
> typedef struct DesignwarePCIEViewport {
> DesignwarePCIERoot *root;
>
> diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
> index 3e8c36e6a7..c07740bfaa 100644
> --- a/hw/pci-host/designware.c
> +++ b/hw/pci-host/designware.c
> @@ -55,6 +55,17 @@
> #define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff)
> #define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C
>
> +static void designware_pcie_root_bus_class_init(ObjectClass *klass, void
> *data)
> +{
> + BusClass *k = BUS_CLASS(klass);
> +
> + /*
> + * Designware has only a single root complex. Enforce the limit on the
> + * parent bus
> + */
> + k->max_dev = 1;
> +}
This seems to be what we do in at least one other PCI host
controller, so
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
