It seems v2.2 has changed fmin/fmax for the fpu as well.
>
> We really should fix that too...
>
>
> r~
>
>
The noprop is implemented in below patch and could be applied to scalar
part
https://patchew.org/QEMU/1597908641-6293-1-git-send-email-chihmin.c...@sifive.com/
Chih-Min Chao
NaN && ft2 == sNaN
The ieee754 spec allows both implementation and some architecture such
as riscv choose differenct defintion in two spec versions.
(riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to
alternative)
Signed-off-by: Chih-Min Chao
---
fpu/softfl
On Fri, Aug 14, 2020 at 1:21 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 7/30/20 2:52 AM, Chih-Min Chao wrote:
> > For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN,
> > The original logic
> > return NaN and set inval
d0 -device virtio-blk-device,drive=hd0
> >
> Log:
> > rom: requested regions overlap (rom phdr #0: bbl.
> > free=0x8000c160, addr=0x000080000000)
> > qemu-system-riscv32: rom check and register reset failed
> >
Try to add "-bios none"
When writing, box the 16bit value with all ones in high part[63:16]
When reading, unbox the 16bit value from 64bit storage and validate it
Signed-off-by: Chih-Min Chao
---
target/riscv/internals.h | 16
target/riscv/translate.c | 15 +++
2 files changed, 31
From: Kito Cheng
All of instructions listed in spec has been implemented. The spec is still
under discussion and not included master branch.
ref:
https://github.com/riscv/riscv-isa-manual/tree/zfh
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
---
target/riscv/cpu.h
226-1-git-send-email-chihmin.c...@sifive.com>
Based-on: <20200724002807.441147-1-richard.hender...@linaro.org>
Chih-Min Chao (2):
target/riscv: add NaN-Boxing helper for half-float
target/riscv: support 'x-k' in cpu option
Kito Cheng (1):
target/riscv: Implement zfh ex
ual/issues/414
Signed-off-by: Chih-Min Chao
---
target/riscv/cpu.c | 4
target/riscv/cpu.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 228b9bd..8ad8782 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -469,6 +469,9 @@ s
64();
> +gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]);
> +
> +/*
> + * Replace bit 31 in rs1 with inverse in rs2.
> + * This formulation retains the nanboxing of rs1.
> + */
> + mask = tcg_const_i64(~MAKE_64BIT_MASK(31, 1
On Thu, Aug 6, 2020 at 3:05 PM LIU Zhiwei wrote:
>
>
> On 2020/8/6 14:09, Chih-Min Chao wrote:
>
> On Fri, Jul 24, 2020 at 2:06 PM LIU Zhiwei wrote:
>
>>
>>
>> On 2020/7/24 11:55, Richard Henderson wrote:
>> > On 7/23/20 7:35 PM, LIU Zhiwei
ans_fsw(DisasContext *ctx, arg_fsw *a)
> {
> +REQUIRE_FPU;
> +REQUIRE_EXT(ctx, RVF);
> TCGv t0 = tcg_temp_new();
> gen_get_gpr(t0, a->rs1);
>
> -REQUIRE_FPU;
> -REQUIRE_EXT(ctx, RVF);
> tcg_gen_addi_tl(t0, t0, a->imm);
>
> tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
> --
> 2.25.1
>
>
>
Reviewed-by: Chih-Min Chao
Chih-Min Chao
> -tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
> -#else
> -tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
> -#endif
> +tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0);
> gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
>
> mark_fs_dirty(ctx);
> --
> 2.25.1
>
>
>
Reviewed-by: Chih-Min Chao
Chih-Min Chao
9.2).
> + *
> + * Here, the result is always nan-boxed, even the canonical nan.
> + */
> +static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
> +{
> +TCGv_i64 t_max = tcg_const_i64(0xull);
> +TCGv_i64 t_nan = tcg_const_i64(0x7fc0ull);
> +
> +tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
> +tcg_temp_free_i64(t_max);
> +tcg_temp_free_i64(t_nan);
> +}
> +
> static void generate_exception(DisasContext *ctx, int excp)
> {
> tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
> --
> 2.25.1
>
>
>
Reviewed-by: Chih-Min Chao
Chih-Min Chao
> return float32_to_uint64(frs1, &env->fp_status);
> }
> #endif
> @@ -233,8 +259,9 @@ uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t
> rs1)
> }
> #endif
>
> -target_ulong helper_fclass_s(uint64_t frs1)
> +target_ulong helper_fclass_s(uint64_t rs1)
> {
> +float32 frs1 = check_nanbox_s(rs1);
> return fclass_s(frs1);
> }
>
> @@ -275,7 +302,8 @@ uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t
> rs1)
>
> uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1)
> {
> -return float32_to_float64(rs1, &env->fp_status);
> +float32 frs1 = check_nanbox_s(rs1);
> +return float32_to_float64(frs1, &env->fp_status);
> }
>
> uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1)
> --
> 2.25.1
>
>
>
Reviewed-by: Chih-Min Chao
Chih-Min Chao
u_i32_i64(cpu_fpr[a->rd], t0);
> #endif
> +gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
>
> mark_fs_dirty(ctx);
> tcg_temp_free(t0);
> --
> 2.25.1
>
>
>
Reviewed-by: Chih-Min Chao
Chih-Min Chao
and simplicity, we nanbox results even when the RVD
> + * extension is not present.
> + */
> +static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
> +{
> + tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
> +}
> +
> static void generate_exception(DisasContext *ctx, int excp)
> {
> tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
> --
> 2.25.1
>
>
>
Reviewed-by: Chih-Min Chao
, I mentioned defining a second function,
> >
> > static inline uint64_t nanbox_h(float16 f)
> > {
> > return f | MAKE_64BIT_MASK(16, 48);
> > }
> >
> > Having two separate functions will, I believe, be easier to use in
> practice.
> >
> Get it. Thanks.
>
> Zhiwei
> >
> > r~
>
>
>
That is what has been implemented in spike. It fills up the Nan-Box when
value is stored back internal structure and
unbox the value with difference floating type (half/single/double/quad).
By the way, I prefer to keeping the suffix to tell different floating
type rather than pass arbitrary
since each floating type belong to each extension.
Reviewed-by: Chih-Min Chao
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alex Bennée
---
fpu/softfloat.c | 34 ++
include/fpu/softfloat.h | 8
2 files changed, 42 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 4466ece..c700a39 100644
---
From: Kito Cheng
Implement them in softfloat and remove local version in riscv
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Acked-by: Alex Bennée
---
include/fpu/softfloat.h | 41 +
target/riscv/vector_helper.c | 25
These patches are separated from riscv vector extension 0.9 patchset.
The set includes
1. alternative NaN handlding
2. float16 comparision APIs.
3. float16 to int8/uint8 conversion APIs
Chih-Min Chao (1):
softfloat: add APIs to handle alternative sNaN propagation
Frank Chang (1
eee754 spec allows both implementation and some architecture such
as riscv choose differenct defintion in two spec versions.
(riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to
alternative)
Signed-off-by: Chih-Min Chao
---
fpu/softfl
On Fri, Jul 10, 2020 at 8:26 PM Alex Bennée wrote:
>
> Alex Bennée writes:
>
> > frank.ch...@sifive.com writes:
> >
> >> From: Kito Cheng
> >>
> >> Signed-off-by: Kito Cheng
> >> Signed-off-by: Chih-Min Chao
> >> Signed-o
On Fri, Jul 10, 2020 at 8:15 PM Alex Bennée wrote:
>
> frank.ch...@sifive.com writes:
>
> > From: Chih-Min Chao
> >
> > Signed-off-by: Chih-Min Chao
> > Signed-off-by: Frank Chang
> > ---
> > fpu/softfloat.c | 68 +
On Tue, Jun 30, 2020 at 3:37 PM LIU Zhiwei wrote:
>
>
> On 2020/6/30 15:31, Chih-Min Chao wrote:
>
> On Sat, Jun 27, 2020 at 5:09 AM LIU Zhiwei wrote:
>
>> Signed-off-by: LIU Zhiwei
>> ---
>> target/riscv/insn_trans/trans_rvd.inc.c | 7 +-
>> tar
74,16 @@ static bool trans_fcvt_l_s(DisasContext *ctx,
> arg_fcvt_l_s *a)
> REQUIRE_EXT(ctx, RVF);
>
> TCGv t0 = tcg_temp_new();
> +TCGv_i64 t1 = tcg_temp_new_i64();
> +tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]);
> +check_nanboxed(ctx, 1, t1);
> +
> gen_set_rm(ctx, a->rm);
> -gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
> +gen_helper_fcvt_l_s(t0, cpu_env, t1);
> gen_set_gpr(a->rd, t0);
> +
> tcg_temp_free(t0);
> +tcg_temp_free_i64(t1);
> return true;
> }
>
> @@ -413,10 +593,16 @@ static bool trans_fcvt_lu_s(DisasContext *ctx,
> arg_fcvt_lu_s *a)
> REQUIRE_EXT(ctx, RVF);
>
> TCGv t0 = tcg_temp_new();
> +TCGv_i64 t1 = tcg_temp_new_i64();
> +tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]);
> +check_nanboxed(ctx, 1, t1);
> +
> gen_set_rm(ctx, a->rm);
> -gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
> +gen_helper_fcvt_lu_s(t0, cpu_env, t1);
> gen_set_gpr(a->rd, t0);
> +
> tcg_temp_free(t0);
> +tcg_temp_free_i64(t1);
> return true;
> }
>
> --
> 2.23.0
>
>
It may be more readable to use local macro to wrap allocation and free of
tcg temp variables. Most functions are two-operands,
some requires one and the other needs three operands. They may be like
#define GEN_ONE_OPERAND \
TCGv_i64 t1 = tcg_temp_new_i64(); \
tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); \
check_nanboxed(ctx, 1, t1);
#define GEN_TWO_OPERAND \
TCGv_i64 t1 = tcg_temp_new_i64(); \
TCGv_i64 t2 = tcg_temp_new_i64(); \
tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); \
tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); \
check_nanboxed(ctx, 2, t1, t2);
#define GEN_THREE_OPERAND \
TCGv_i64 t1 = tcg_temp_new_i64(); \
TCGv_i64 t2 = tcg_temp_new_i64(); \
TCGv_i64 t3 = tcg_temp_new_i64(); \
tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); \
tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); \
tcg_gen_mov_i64(t3, cpu_fpr[a->rs3]); \
check_nanboxed(ctx, 3, t1, t2, t3);
#define FREE_ONE_OPERAND \
tcg_temp_free_i64(t1);
#define FREE_TWO_OPERAND \
tcg_temp_free_i64(t1); \
tcg_temp_free_i64(t2);
#define FREE_THREE_OPERAND \
tcg_temp_free_i64(t1); \
tcg_temp_free_i64(t2); \
tcg_temp_free_i64(t3);
Chih-Min Chao
t; +}
> +
> +va_end(valist);
> +tcg_temp_free_i64(cond1);
>
forget to remove ?
> +tcg_temp_free_i64(t_nan);
> +tcg_temp_free_i64(t_max);
> + }
> +}
> +
> static void generate_exception(DisasContext *ctx, int excp)
> {
> tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
> --
> 2.23.0
>
>
Chih-Min Chao
ping ? Could this be merged ?
Chih-Min Chao
On Wed, Jan 29, 2020 at 3:43 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 1/27/20 4:37 PM, Ian Jiang wrote:
> > The function that makes NaN-boxing when a 32-bit value is assigned
> > to a 64-bit FP regis
On Thu, Sep 12, 2019 at 6:39 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 9/11/19 10:51 AM, Chih-Min Chao wrote:
> > Could the VLEN be configurable in cpu initialization but not fixed in
> > compilation phase ?
> > Take the integer element as
On Wed, Sep 11, 2019 at 2:38 PM liuzhiwei wrote:
> From: LIU Zhiwei
>
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/Makefile.objs | 2 +-
> target/riscv/helper.h | 3 +
> target/riscv/insn32.decode | 5 ++
> target/riscv/insn_trans/trans_rvv
write_fcsr
> },
> -
> + /* Vector CSRs */
> +[CSR_VSTART] = { any, read_vstart, write_vstart
> },
> +[CSR_VXSAT] = { any, read_vxsat, write_vxsat
>},
> +[CSR_VXRM] ={ any, read_vxrm, write_vxrm
> },
> +[CSR_VL] = { any, read_vl
> },
> +[CSR_VTYPE] = { any, read_vtype
>},
> /* User Timers and Counters */
> [CSR_CYCLE] = { ctr, read_instret
> },
> [CSR_INSTRET] = { ctr, read_instret
> },
> --
> 2.7.4
>
>
>
Reviewed-by: Chih-Min Chao
+#define RVV RV('V')
>
> /* S extension denotes that Supervisor mode exists, however it is possible
> to have a core that support S mode but does not have an MMU and there
> @@ -250,6 +251,7 @@ typedef struct RISCVCPU {
> bool ext_c;
> bool ext_s;
> bool ext_u;
> +bool ext_v;
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> --
> 2.7.4
>
>
> Reviewed-by: Chih-Min Chao
On Wed, Sep 11, 2019 at 2:35 PM liuzhiwei wrote:
> From: LIU Zhiwei
>
> Signed-off-by: LIU Zhiwei
> ---
> target/riscv/cpu.h | 28
> 1 file changed, 28 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0adb307..c992b1d 100644
> --- a/ta
target_ulong vstvec;
> +target_ulong vsscratch;
> +target_ulong vsepc;
> +target_ulong vscause;
> +target_ulong vstval;
> +target_ulong vsatp;
> +
> target_ulong scounteren;
> target_ulong mcounteren;
>
> --
> 2.22.0
>
>
Reviewed-by: Chih-Min Chao
On Sat, Aug 24, 2019 at 7:50 AM Alistair Francis
wrote:
> Signed-off-by: Alistair Francis
> ---
> target/riscv/cpu.h| 2 ++
> target/riscv/cpu_bits.h | 6 ++
> target/riscv/cpu_helper.c | 23 +++
> 3 files changed, 31 insertions(+)
>
> diff --git a/target/ris
On Sat, Aug 24, 2019 at 7:41 AM Alistair Francis
wrote:
> Signed-off-by: Alistair Francis
> ---
> target/riscv/cpu.h| 4
> target/riscv/cpu_bits.h | 6 ++
> target/riscv/cpu_helper.c | 23 +++
> 3 files changed, 33 insertions(+)
>
> diff --git a/target/r
gt; to have a core that support S mode but does not have an MMU and there
> --
> 2.22.0
>
>
> Reviewed-by: Chih-Min Chao
On Mon, Aug 19, 2019 at 9:47 PM liuzhiwei wrote:
>
> On 2019/8/17 上午1:29, Alistair Francis wrote:
> > On Thu, Aug 15, 2019 at 8:39 PM liuzhiwei wrote:
> >> Hi, Palmer
> >>
> >> When Michael Clark still was the maintainer of RISCV QEMU, he wrote in
> the mail list, "the CLIC interrupt controller
On Wed, Aug 7, 2019 at 6:11 PM Bin Meng wrote:
> On Wed, Aug 7, 2019 at 4:54 PM Chih-Min Chao
> wrote:
> >
> >
> >
> > On Wed, Aug 7, 2019 at 3:49 PM Bin Meng wrote:
> >>
> >> Current SiFive PRCI model only works with sifive_e machine, as it
&
On Thu, Aug 8, 2019 at 7:29 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
> On Thu, Aug 8, 2019 at 11:52 AM liuzhiwei wrote:
>
> > Hi all,
> >
> > My workmate and I have been working on Vector & Dsp extension, and
> > I'd like to share develop status with folks.
> >
> > T
FIVE_U_UART0] ={ 0x1001, 0x1000 },
> +[SIFIVE_U_UART1] ={ 0x10011000, 0x1000 },
> [SIFIVE_U_DRAM] = { 0x8000,0x0 },
> [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
> };
> --
> 2.7.4
>
>
>
By the way, OpenSBI also needs a patch to fix the same problem.
Reviewed-by: Chih-Min Chao
etprop_cell(fdt, "/chosen",
> +qemu_fdt_setprop_cell(s->fdt, "/chosen",
> "linux,initrd-start", start);
> -qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
> +qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
>end);
> }
> }
> --
> 2.7.4
>
>
>
Reviewed-by: Chih-Min Chao
&start);
> +qemu_fdt_setprop_cell(s->fdt, "/chosen",
> + "linux,initrd-start", start);
> +qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
> + end);
> +}
> }
>
> /* reset vector */
> --
> 2.7.4
>
>
>
virt also does the same thing.
Reviewed-by: Chih-Min Chao
e506b 100644
> --- a/include/hw/riscv/sifive_e_prci.h
> +++ b/include/hw/riscv/sifive_e_prci.h
> @@ -47,6 +47,8 @@ enum {
> SIFIVE_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
> };
>
> +#define SIFIVE_E_PRCI_REG_SIZE 0x1000
> +
> #define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci"
>
> #define SIFIVE_E_PRCI(obj) \
> --
> 2.7.4
>
>
> Reviewed-by: Chih-Min Chao
xosccfg = (SIFIVE_PRCI_HFXOSCCFG_RDY | SIFIVE_PRCI_HFXOSCCFG_EN);
> s->pllcfg = (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS |
> SIFIVE_PRCI_PLLCFG_LOCK);
> s->plloutdiv = SIFIVE_PRCI_PLLOUTDIV_DIV1;
> --
> 2.7.4
>
>
Reviewed-by: Chih-Min Chao
On Wed, Aug 7, 2019 at 3:49 PM Bin Meng wrote:
> Current SiFive PRCI model only works with sifive_e machine, as it
> only emulates registers or PRCI block in the FE310 SoC.
>
> Rename the file name to make it clear that it is for sifive_e.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2: Non
; rm -rf seabios/.config seabios/out seabios/builds
> --
> 2.7.4
>
>
Reviewed-by: Chih-Min Chao
scv_cpu_fp_enabled(env)) {
> return -1;
> }
> env->mstatus |= MSTATUS_FS;
> @@ -307,6 +307,7 @@ static int write_mstatus(CPURISCVState *env, int
> csrno, target_ulong val)
> {
> target_ulong mstatus = env->mstatus;
> target_ulong mask = 0;
> + int dirty;
>
> /* flush tlb on mstatus fields that affect VM */
> if (env->priv_ver <= PRIV_VERSION_1_09_1) {
> @@ -340,8 +341,9 @@ static int write_mstatus(CPURISCVState *env, int
> csrno, target_ulong val)
>
> mstatus = (mstatus & ~mask) | (val & mask);
>
> -int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
> -((mstatus & MSTATUS_XS) == MSTATUS_XS);
> +dirty = (riscv_cpu_fp_enabled(env) &&
> + ((mstatus & MSTATUS_FS) == MSTATUS_FS)) |
> +((mstatus & MSTATUS_XS) == MSTATUS_XS);
> mstatus = set_field(mstatus, MSTATUS_SD, dirty);
> env->mstatus = mstatus;
>
> --
> 2.22.0
>
>
> Reviewed-by: Chih-Min Chao
SATP32_PPN
> -#endif
> -#if defined(TARGET_RISCV64)
> -#define HGATP_MODE SATP64_MODE
> -#define HGATP_ASID SATP64_ASID
> -#define HGATP_PPN SATP64_PPN
> -#endif
> -
> /* Performance Counters */
> #define CSR_MHPMCOUNTER30xb03
> #define CSR_MHPMCOUNTER40xb04
> --
> 2.22.0
>
> Reviewed-by: Chih-Min Chao
On Sat, Aug 3, 2019 at 8:27 AM Bin Meng wrote:
> Some of the SoC IP block sizes are wrong. Correct them according
> to the FE310 manual.
>
> Signed-off-by: Bin Meng
> ---
>
> hw/riscv/sifive_e.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b
On Wed, Jul 31, 2019 at 2:41 AM Alistair Francis
wrote:
> On Mon, Jul 29, 2019 at 8:19 AM Chih-Min Chao
> wrote:
> >
> >
> > On Fri, Jul 26, 2019 at 2:56 AM Alistair Francis <
> alistair.fran...@wdc.com> wrote:
> >>
> >> From: Atish Patr
tate *sifive_plic_create(hwaddr addr, char *hart_config,
> uint32_t num_sources, uint32_t num_priorities,
> uint32_t priority_base, uint32_t pending_base,
> --
> 2.22.0
>
>
Reviewed-by: Chih-Min Chao
On Fri, Jul 26, 2019 at 2:55 AM Alistair Francis
wrote:
> Let's creaate a function that tests if floating point support is
> enabled. We can then protect all floating point operations based on if
> they are enabled.
>
> This patch so far doesn't change anything, it's just preparing for the
> Hype
On Fri, Jul 26, 2019 at 2:56 AM Alistair Francis
wrote:
> From: Atish Patra
>
> As per the RISC-V spec, Floating Point registers are named as f0..f31
> so lets fix the register names accordingly.
>
> Signed-off-by: Atish Patra
> Signed-off-by: Alistair Francis
> ---
> target/riscv/cpu.c | 8 +
On Fri, Jul 26, 2019 at 2:55 AM Alistair Francis
wrote:
> Update the Hypervisor CSR addresses to match the v0.4 spec.
>
> Signed-off-by: Alistair Francis
> ---
> target/riscv/cpu_bits.h | 35 ++-
> 1 file changed, 18 insertions(+), 17 deletions(-)
>
> diff --git
On Thu, Jul 25, 2019 at 8:12 AM Alistair Francis
wrote:
> On Tue, Jul 23, 2019 at 11:46 PM Chih-Min Chao
> wrote:
> >
> > Similar to the mips + malta test, it boots a Linux kernel on a virt
> > board and verify the serial is working. Also, it relies on the serial
>
m/groeck/linux-build-test/rootfs/riscv64/rootfs.cpio.gz
(the repo is also used in mips target acceptance)
Signed-off-by: Chih-Min Chao
---
.travis.yml| 2 +-
tests/acceptance/boot_linux_console.py | 67 ++
2 files changed, 68 inser
On Thu, Jul 18, 2019 at 11:34 PM Alistair Francis
wrote:
> On Thu, Jul 18, 2019 at 8:00 AM Chih-Min Chao
> wrote:
> >
> >
> >
> > On Thu, Jul 18, 2019 at 6:47 AM Alistair Francis
> wrote:
> >>
> >> On Tue, Jul 16, 2019 at 10:21 PM Chih-Min Cha
On Thu, Jul 18, 2019 at 6:47 AM Alistair Francis
wrote:
> On Tue, Jul 16, 2019 at 10:21 PM Chih-Min Chao
> wrote:
> >
> >
> >
> > On Wed, Jul 17, 2019 at 6:59 AM Alistair Francis
> wrote:
> >>
> >> On Tue, Jul 16, 2019 at 2:50 PM Philippe Mat
On Wed, Jul 17, 2019 at 6:59 AM Alistair Francis
wrote:
> On Tue, Jul 16, 2019 at 2:50 PM Philippe Mathieu-Daudé
> wrote:
> >
> > On 7/16/19 10:43 PM, Alistair Francis wrote:
> > > On Tue, Jul 16, 2019 at 6:56 AM Chih-Min Chao
> wrote:
> > >>
>
On Wed, Jul 17, 2019 at 8:17 AM Alistair Francis
wrote:
> On Mon, Jul 15, 2019 at 5:00 AM Peter Maydell
> wrote:
> >
> > On Fri, 7 Jun 2019 at 23:03, Alistair Francis
> wrote:
> > > At the moment this spec is in a draft state and is subject to change.
> As
> > > QEMU is extreamly useful in earl
On Tue, Jul 16, 2019 at 12:34 AM Alistair Francis
wrote:
> On Mon, Jul 15, 2019 at 6:02 AM Philippe Mathieu-Daudé
> wrote:
> >
> > On 7/15/19 1:09 PM, Chih-Min Chao wrote:
> > > On Mon, Jul 15, 2019 at 5:15 PM Philippe Mathieu-Daudé
> > > mailto:phi...@redh
+--
> target/riscv/csr.c| 216 ++++++++-
> target/riscv/insn32.decode| 23 +-
> .../riscv/insn_trans/trans_privileged.inc.c | 40 ++
> target/riscv/op_helper.c | 71 ++-
> target/riscv/translate.c | 26 +
> 11 files changed, 839 insertions(+), 102 deletions(-)
>
> --
> 2.21.0
>
>
tested with Linux kernel v5.2 and related opensbi/xvisor branches
described above.
Tested-by: Chih-Min Chao
On Mon, Jul 15, 2019 at 5:15 PM Philippe Mathieu-Daudé
wrote:
> On 7/15/19 11:08 AM, Chih-Min Chao wrote:
> > Similar to the mips + malta test, it boots a Linux kernel on a virt
> > board and verify the serial is working. Also, it relies on the serial
> > device set
eck/linux-build-test/rootfs/riscv64/rootfs.cpio.gz
(the repo is also used in mips target acceptance)
Signed-off-by: Chih-Min Chao
---
.travis.yml| 2 +-
tests/acceptance/boot_linux_console.py | 66 ++
2 files changed, 67 insertions(+),
On Thu, Jul 11, 2019 at 4:23 AM Cleber Rosa wrote:
> On Wed, Jul 10, 2019 at 10:50:23AM -0700, Chih-Min Chao wrote:
> > Similar to the mips + malta test, it boots a Linux kernel on a virt
> > board and verify the serial is working. Also, it relies on the serial
> > devi
On Thu, Jul 11, 2019 at 2:53 AM Alistair Francis
wrote:
> On Wed, Jul 10, 2019 at 10:51 AM Chih-Min Chao
> wrote:
> >
> > Similar to the mips + malta test, it boots a Linux kernel on a virt
> > board and verify the serial is working. Also, it relies on the serial
>
use of the "arch:riscv64" tags.
Alternatively, this test can be run using:
$ avocado run -t arch:riscv64 tests/acceptance
Signed-off-by: Chih-Min Chao
---
tests/acceptance/boot_linux_console.py | 40 ++
1 file changed, 40 insertions(+)
diff --gi
From: Jim Wilson
Signed-off-by: Jim Wilson
Signed-off-by: Chih-Min Chao
---
configure | 1 +
gdb-xml/riscv-32bit-cpu.xml | 47 +
gdb-xml/riscv-32bit-csr.xml | 250
gdb-xml/riscv-32bit-fpu.xml | 50 +
4 files
From: Jim Wilson
Signed-off-by: Jim Wilson
Signed-off-by: Chih-Min Chao
---
configure | 1 +
gdb-xml/riscv-32bit-fpu.xml | 6 +-
gdb-xml/riscv-64bit-cpu.xml | 47 +
gdb-xml/riscv-64bit-csr.xml | 250
gdb-xml/riscv
first
csr register # become 69. We register extra register on gdb to correct
csr offset calculation
Signed-off-by: Jim Wilson
Signed-off-by: Chih-Min Chao
---
target/riscv/cpu.c | 9 +-
target/riscv/cpu.h | 2 +
target/riscv/gdbstub.c | 350
This is the 5th version of the patch set, based on the Jim's previous work,
http://lists.nongnu.org/archive/html/qemu-riscv/2019-02/msg00059.html
v4 -> v5:
- rebase 7074ab1
- update the register xml files to gdb 8.3
- refine the fpu control registers, fflags/frm/fcsr
From: Jim Wilson
Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function
to set it. Disable mode checks when debugger field true.
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
Message-Id: <20190212230903.9215-1-j...@sifive.com>
---
target/riscv/cpu.h | 5 +
targ
From: Jim Wilson
This adds some missing CSR_* register macros, and documents some as being
priv v1.9.1 specific.
Signed-off-by: Jim Wilson
Reviewed-by: Alistair Francis
Message-Id: <20190212230830.9160-1-j...@sifive.com>
---
target/riscv/cpu_bits.h | 35 +--
1
Signed-off-by: Chih-Min Chao
---
ui/console.c | 4 ++--
ui/spice-display.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/ui/console.c b/ui/console.c
index b15ca87..d8d268c 100644
--- a/ui/console.c
+++ b/ui/console.c
@@ -269,7 +269,7 @@ void graphic_hw_invalidate
reported by checkpatch.pl
Signed-off-by: Chih-Min Chao
---
ui/vnc-auth-vencrypt.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/ui/vnc-auth-vencrypt.c b/ui/vnc-auth-vencrypt.c
index a420ccb..65f1afa 100644
--- a/ui/vnc-auth-vencrypt.c
+++ b/ui/vnc-auth-vencrypt.c
Signed-off-by: Chih-Min Chao
---
hw/display/qxl.c | 2 +-
ui/spice-display.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/display/qxl.c b/hw/display/qxl.c
index b6d65b9..0cd314c 100644
--- a/hw/display/qxl.c
+++ b/hw/display/qxl.c
@@ -696,7 +696,7 @@ static
don't mix tab and space. The rule is 4 spaces
Signed-off-by: Chih-Min Chao
---
include/qemu/bitops.h | 61 ++-
1 file changed, 31 insertions(+), 30 deletions(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 90ca8df..8a
patch 1-2
fix the coding style related to space indent and brance position
patch 3-5
remove the 'struct' from the type which has been typedef
Chih-Min Chao (5):
bitops : fix coding style
ui/vnc : fix coding style
ui/vnc : remove 'struct' of &
Signed-off-by: Chih-Min Chao
---
ui/vnc-auth-vencrypt.c | 4 ++--
ui/vnc-tls.c | 10 +-
ui/vnc-ws.c| 4 ++--
ui/vnc.c | 2 +-
4 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/ui/vnc-auth-vencrypt.c b/ui/vnc-auth-vencrypt.c
index
On Wed, Dec 24, 2014 at 1:50 AM, Peter Maydell
wrote:
> On 23 December 2014 at 16:25, Chih-Min Chao wrote:
> > Update the reference manual version to DDI0487A_c
> >
> > Instruction set encoding is moved from C3 to C4
> > Instruction set Description is move
The changes are based on reference manual version, DDI0487A_c,
and most of them are SIMD related sub-chapter
Signed-off-by: Chih-Min Chao
---
target-arm/translate-a64.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/target-arm
Update the reference manual version to DDI0487A_c
Instruction set encoding is moved from C3 to C4
Instruction set Description is moved from C5/C6 to C6/C7
Signed-off-by: Chih-Min Chao
---
target-arm/helper-a64.c| 2 +-
target-arm/translate-a64.c | 228
Another good slide for PQemu
http://people.cs.nctu.edu.tw/~chenwj/slide/QEMU/PQEMU_presentation_(IIS_Sinica_2)_.pptx
On Wed, Nov 26, 2014 at 5:31 PM, Mark Burton
wrote:
>
>
> Hi all,
>
> We are now actively going to pursue TCG Multithreading to improve the
> performance of the TCG for Qemu model
Just change what I have used and looked into.
There are no other special reasons.
On Fri, Sep 5, 2014 at 2:05 AM, Peter Maydell
wrote:
> On 4 September 2014 19:01, Chih-Min Chao wrote:
> > CPUARMState is one of parameter used by
> > is_a64
> >
CPUARMState is one of parameter used by
is_a64
arm_feature
arm_el_is_aa64
They only read it without any side effect and shold be changed to
const parameter
Signed-off-by: Chih-Min Chao
---
target-arm/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3
Don't use internal member but availabel wrapper function to
test status
Signed-off-by: Chih-Min Chao
---
hw/arm/boot.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index e32f2f4..26bc25f 100644
--- a/hw/arm/boot.c
+++ b/h
make CPUARMState const to attribute checking functions and use them
to reduce internal status exposure
Chih-Min Chao (2):
target-arm : make parameter of feature/status checking function const
target-arm : use aarch64 mode testing wrapper
hw/arm/boot.c| 4 ++--
target-arm/cpu.h
On Thu, Dec 8, 2011 at 6:58 PM, Peter Maydell wrote:
> On 7 December 2011 10:45, Dmitry Solodkiy wrote:
>> Dear Peter,
>>
>> Orion, s5pc210 and Exynos4210 are aliases for the same hardware chip.
>> We decided that s5pc210 is more informative than exynos4 (there are
>> many hardware models start
On Sun, Oct 30, 2011 at 7:39 PM, 陳韋任 wrote:
> Hi, all
>
> I am looking into QEMU's implementation for ARM NEON instructions
> (target-arm/neon_helper.c). Some helper functions will do mask
> operation, neon_add_u8, for example. I thought simply adding a and b
> is enough and can't figure out why
On Thu, Sep 2, 2010 at 6:41 PM, Andrea Galeazzi wrote:
> Hi every body,
> I'm a newbie about the qemu word but I'd like to emulate the versatile ARM
> platform. In particular I'm very interested in knowing how much the
> emulation of PL110 LCD controller fits the real hardware. Are some features
>
2010/8/21 S W
> Hi there
>
> I made an ARM Linux2.6.10 image(zImage) and I tried to run it on QEMU using
> the following command.
>
> qemu-system-arm -kernel zImage -nographic
>
> I got an error message like:
>
> CPU #0:
> R00= R01=0113 R02=0100 R03=
> R04= R05=00
Signed-off-by: Chih-Min Chao
---
target-arm/translate.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index a28e2ff..6fcdd7e 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -561,7 +561,7 @@ static
Signed-off-by: Chih-Min Chao
---
target-arm/helper.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 63e5dc7..2dd64d9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2047,7 +2047,7 @@ static inline
The three patches focuse on Bugs 595906 & Bug 591320. The first is related to
Bug 595906 and the other solve Bug 591320.
The series are also attached in the threads, listed below
https://bugs.launchpad.net/qemu/+bug/595906
https://bugs.launchpad.net/qemu/+bug/591320
[PATCH 1/3] target-arm:
Signed-off-by: Chih-Min Chao
---
target-arm/op_addsub.h |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-arm/op_addsub.h b/target-arm/op_addsub.h
index 29f77ba..c02c92a 100644
--- a/target-arm/op_addsub.h
+++ b/target-arm/op_addsub.h
@@ -73,8 +73,8
Signed-off-by: Chih-Min Chao
---
aio.c|2 +-
gdbstub.c|2 +-
hw/lance.c |2 +-
hw/pcnet.c |2 +-
hw/virtio-9p.c |2 +-
migration-exec.c |2 +-
migration-fd.c |4 +-
migration-tcp.c |2 +-
migration-unix.c |2
On Sat, May 29, 2010 at 1:43 AM, cmchao wrote:
>
> Signed-off-by: cmchao
> ---
> hw/omap.h | 36
> hw/omap1.c | 10 +-
> hw/omap2.c |6 +++---
> 3 files changed, 8 insertions(+), 44 deletions(-)
>
> diff --git a/hw/omap.h b/hw/omap.h
> inde
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