zfh extension is still a draft and is not included in master spec. The
related field, 'k', in MISA is also undecided but has been discussed in
reference link.
ref:
zfh spec: https://github.com/riscv/riscv-isa-manual/tree/zfh
misa field: https://github.com/riscv/riscv-isa-manual/issues/414
Signed-off-by: Chih-Min Chao <chihmin.c...@sifive.com>
---
target/riscv/cpu.c | 4 ++++
target/riscv/cpu.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 228b9bd..8ad8782 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -469,6 +469,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
set_vext_version(env, vext_version);
}
+ if (cpu->cfg.ext_k) {
+ target_misa |= RVZfh;
+ }
set_misa(env, RVXLEN | target_misa);
}
@@ -509,6 +512,7 @@ static Property riscv_cpu_properties[] = {
/* This is experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
+ DEFINE_PROP_BOOL("x-k", RISCVCPU, cfg.ext_k, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6a077c1..bdef2a8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -281,6 +281,7 @@ typedef struct RISCVCPU {
bool ext_u;
bool ext_h;
bool ext_v;
+ bool ext_k;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
--
2.7.4
