On Sat, Aug 24, 2019 at 7:45 AM Alistair Francis <alistair.fran...@wdc.com>
wrote:
> As the MIP CSR is 32-bits to allow atomic_read on 32-bit hosts the vsip
> is 32-bit as well.
>
> Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
> ---
> target/riscv/cpu.h | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 3a95c41428..4c342e7a79 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -154,6 +154,23 @@ struct CPURISCVState {
> target_ulong mcause;
> target_ulong mtval; /* since: priv-1.10.0 */
>
> + /* Hypervisor CSRs */
> + target_ulong hstatus;
> + target_ulong hedeleg;
> + target_ulong hideleg;
> + target_ulong hgatp;
> +
> + /* Virtual CSRs */
> + target_ulong vsstatus;
> + uint32_t vsip;
> + target_ulong vsie;
> + target_ulong vstvec;
> + target_ulong vsscratch;
> + target_ulong vsepc;
> + target_ulong vscause;
> + target_ulong vstval;
> + target_ulong vsatp;
> +
> target_ulong scounteren;
> target_ulong mcounteren;
>
> --
> 2.22.0
>
>
Reviewed-by: Chih-Min Chao <chihmin.c...@sifive.com>
