On Fri, Jul 24, 2020 at 8:28 AM Richard Henderson < richard.hender...@linaro.org> wrote:
> Make sure that all results from inline single-precision scalar > operations are properly nan-boxed to 64-bits. > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > --- > target/riscv/insn_trans/trans_rvf.inc.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/target/riscv/insn_trans/trans_rvf.inc.c > b/target/riscv/insn_trans/trans_rvf.inc.c > index c7057482e8..264d3139f1 100644 > --- a/target/riscv/insn_trans/trans_rvf.inc.c > +++ b/target/riscv/insn_trans/trans_rvf.inc.c > @@ -167,6 +167,7 @@ static bool trans_fsgnj_s(DisasContext *ctx, > arg_fsgnj_s *a) > tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], > cpu_fpr[a->rs1], > 0, 31); > } > + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); > mark_fs_dirty(ctx); > return true; > } > @@ -183,6 +184,7 @@ static bool trans_fsgnjn_s(DisasContext *ctx, > arg_fsgnjn_s *a) > tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31); > tcg_temp_free_i64(t0); > } > + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); > mark_fs_dirty(ctx); > return true; > } > @@ -199,6 +201,7 @@ static bool trans_fsgnjx_s(DisasContext *ctx, > arg_fsgnjx_s *a) > tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); > tcg_temp_free_i64(t0); > } > + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); > mark_fs_dirty(ctx); > return true; > } > @@ -369,6 +372,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, > arg_fmv_w_x *a) > #else > tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0); > #endif > + gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); > > mark_fs_dirty(ctx); > tcg_temp_free(t0); > -- > 2.25.1 > > > Reviewed-by: Chih-Min Chao <chihmin.c...@sifive.com> Chih-Min Chao
