On Tue, Jun 09, 2015 at 02:30:02PM -0700, Anuj Phogat wrote:
> On Tue, Jun 2, 2015 at 2:51 PM, Anuj Phogat wrote:
> > Patch sets the alignments for texture and renderbuffer surfaces.
> >
> > V3: Make changes inside horizontal_alignment() and
> > vertical_alignment() (Topi)
> >
> > Signed-off-b
On Wed, Jun 17, 2015 at 10:36:04PM -0700, Kenneth Graunke wrote:
> This was originally only used by the vertex shader, but it's now used by
> the geometry shader as well, and will also eventually be used for
> tessellation control and evaluation shaders.
>
> I suspect it will be easier to find in
On Thu, Jun 04, 2015 at 05:35:11PM -0700, Ben Widawsky wrote:
> On Wed, Jun 03, 2015 at 09:32:55PM +0300, Pohjolainen, Topi wrote:
> > On Wed, Jun 03, 2015 at 09:21:11PM +0300, Topi Pohjolainen wrote:
> > > Shader programs are cached per stage (FS, VS, GS) using the
> >
On Mon, Jun 22, 2015 at 01:28:12PM +0300, Pohjolainen, Topi wrote:
> On Thu, Jun 04, 2015 at 05:35:11PM -0700, Ben Widawsky wrote:
> > On Wed, Jun 03, 2015 at 09:32:55PM +0300, Pohjolainen, Topi wrote:
> > > On Wed, Jun 03, 2015 at 09:21:11PM +0300, Topi Pohjolainen wrote:
>
On Thu, Jun 18, 2015 at 05:51:35PM -0700, Jason Ekstrand wrote:
> This doesn't affect instructions allocated using the builder.
> ---
> src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
Reviewed-by: Topi Pohjolainen
>
> diff --git
On Thu, Jun 18, 2015 at 05:51:36PM -0700, Jason Ekstrand wrote:
> We want to move these into the builder so that they know the current
> builder's dispatch width. This will be needed by a later commit.
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 52 ++
> src/mesa/drivers/dri/i
On Thu, Jun 18, 2015 at 05:51:39PM -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Topi Pohjolainen
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
> b/src/mesa/drivers/dri/i965/brw_fs
On Thu, Jun 18, 2015 at 05:51:43PM -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_fs_builder.h | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h
> b/src/mesa/drivers/dri/i965/brw_fs_builder.h
> index 7d
On Thu, Jun 18, 2015 at 05:51:37PM -0700, Jason Ekstrand wrote:
> Previously, we were just depending on register widths to ensure that
> various things were exec_size of 1 etc. Now, we do so explicitly using the
> builder.
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 14 --
> 1 file
On Thu, Jun 18, 2015 at 05:51:46PM -0700, Jason Ekstrand wrote:
> As of now, the width field is no longer used for anything. The width field
> "seemed like a good idea at the time" but is actually entirely redundant
> with the instruction's execution size. Initially, it gave us the ability
> to e
On Wed, Jun 24, 2015 at 05:57:13PM -0700, Anuj Phogat wrote:
> On Wed, Jun 24, 2015 at 3:51 PM, Nanley Chery wrote:
> > From: Nanley Chery
> >
> > Although the horizontal and vertical alignment fields are ignored here,
> > 0 is a reserved value for them and may cause undefined behavior. Change
>
On Thu, Jun 25, 2015 at 08:40:33AM -0700, Nanley Chery wrote:
> On Thu, Jun 25, 2015 at 12:37 AM, Pohjolainen, Topi
> wrote:
> > On Wed, Jun 24, 2015 at 05:57:13PM -0700, Anuj Phogat wrote:
> >> On Wed, Jun 24, 2015 at 3:51 PM, Nanley Chery
> >> wr
On Thu, Jun 25, 2015 at 01:24:53PM -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 42
> src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
> src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 2 +-
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 5
On Thu, Jun 25, 2015 at 09:17:38AM -0700, Kenneth Graunke wrote:
> This ports over Chris Forbes' equivalent fixes in gen7_misc_state.c
> from commit 77d55ef4819436ebbf9786a1e720ec00707bbb19.
>
> No Piglit changes on Sandybridge.
>
> Signed-off-by: Kenneth Graunke
Reviewed-by: Topi Pohjolainen
On Fri, Jun 26, 2015 at 10:54:48AM -0400, Ilia Mirkin wrote:
> On Fri, Jun 26, 2015 at 10:50 AM, Topi Pohjolainen
> wrote:
> > This is stimulating the shader binary re-use logic in i965 buffer
> > object uploading. Without relaxing the current constraints there
> > will be two identical copies in
On Wed, Jul 01, 2015 at 03:03:31PM -0700, Kenneth Graunke wrote:
> Jason plumbed this through a while back in the FS backend, but
> apparently we were just passing NULL in the vec4 backend.
>
> This patch passes brw in as intended.
>
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri
On Wed, Jul 01, 2015 at 03:03:32PM -0700, Kenneth Graunke wrote:
> This patch makes us only issue the performance warning about register
> spilling if we actually spilled registers. We also use scratch space
> for indirect addressing and the like.
>
> This is basically commit c51163b0cf7aff0375b1
On Wed, Jul 01, 2015 at 03:03:33PM -0700, Kenneth Graunke wrote:
> This is more consistent with how we do it in the FS backend, and reduces
> a tiny bit of duplication. It'll also allow for a bit more tidying.
And it also makes it clearer that code generation doesn't have anything to do
with the
On Wed, Jul 01, 2015 at 03:03:34PM -0700, Kenneth Graunke wrote:
> Nothing outside of vec4_visitor uses it, so we may as well keep it
> internal.
>
> Commit db9c915abcc5ad78d2d11d0e732f04cc94631350 for the vec4 backend.
>
> (The empty class will be going away soon.)
>
> Signed-off-by: Kenneth Gr
On Wed, Jul 01, 2015 at 03:03:35PM -0700, Kenneth Graunke wrote:
> At this point, the brw_vs_compile structure only contains the key and
> gl_vertex_program pointer. We may as well pass and store them directly;
> it's simpler and more convenient (key-> instead of vs_compile->key...).
>
> Signed-o
On Fri, Jul 03, 2015 at 11:29:33AM +0300, Pohjolainen, Topi wrote:
> On Wed, Jul 01, 2015 at 03:03:35PM -0700, Kenneth Graunke wrote:
> > At this point, the brw_vs_compile structure only contains the key and
> > gl_vertex_program pointer. We may as well pass and store them dir
On Wed, Jul 01, 2015 at 03:03:36PM -0700, Kenneth Graunke wrote:
> After tearing it out another level or two, and just passing the key and
> vp directly, we can finally remove this struct. It also eliminates a
> pointless memcpy() of the key.
>
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/
On Fri, Jul 03, 2015 at 09:29:16AM -0700, Kenneth Graunke wrote:
> On Friday, July 03, 2015 10:50:52 AM Pohjolainen, Topi wrote:
> > On Wed, Jul 01, 2015 at 03:03:31PM -0700, Kenneth Graunke wrote:
> > > Jason plumbed this through a while back in the FS backend, but
> > &
On Mon, Jul 13, 2015 at 04:15:02PM -0700, Matt Turner wrote:
> ---
> src/mesa/drivers/dri/i965/brw_curbe.c | 2 +-
> src/mesa/drivers/dri/i965/brw_draw_upload.c | 44
> ++---
> 2 files changed, 23 insertions(+), 23 deletions(-)
Reviewed-by: Topi Pohjolainen
__
On Tue, Jul 14, 2015 at 04:48:19PM -0700, Ben Widawsky wrote:
> On Wed, Jul 01, 2015 at 02:46:32PM +0300, Topi Pohjolainen wrote:
> > Signed-off-by: Topi Pohjolainen
>
> I swear I am not trying to nitpick but I don't actually understand what your
> goal of the patch is. Could you maybe elaborate
On Sat, Oct 10, 2015 at 08:09:01AM -0700, Jason Ekstrand wrote:
> This commit removes all dependence on GL state by getting rid of the
> brw_context parameter and the GL data structures.
>
> v2 (Jason Ekstrand):
>- Patch use_legacy_snorm_formula through as a function argument rather
> tha
On Wed, Oct 14, 2015 at 11:25:40AM +0300, Pohjolainen, Topi wrote:
> On Sat, Oct 10, 2015 at 08:09:01AM -0700, Jason Ekstrand wrote:
> > This commit removes all dependence on GL state by getting rid of the
> > brw_context parameter and the GL data structures.
> >
&
On Sat, Oct 10, 2015 at 08:05:59AM -0700, Jason Ekstrand wrote:
> This is really an input into the shader compiler so it kind of makes sense
> in the key. Also, given where it's placed into the key, it doesn't
> actually make it any bigger.
>
> v2 (Jason Ekstrand):
>- Rebase on top of the com
On Wed, Oct 14, 2015 at 11:39:03AM +0200, Neil Roberts wrote:
> Ben Widawsky writes:
>
> > The impetus for this patch comes from a seemingly benign statement within
> > the
> > spec (quoted within the patch). For me, this patch was at some point
> > critical
> > for getting stable piglit result
On Wed, Oct 14, 2015 at 09:54:43AM -0700, Ben Widawsky wrote:
> On Wed, Oct 14, 2015 at 02:43:24PM +0300, Pohjolainen, Topi wrote:
> > On Wed, Oct 14, 2015 at 11:39:03AM +0200, Neil Roberts wrote:
> > > Ben Widawsky writes:
> > >
> > > > The impetus for t
On Wed, Oct 14, 2015 at 11:53:37AM -0700, Jason Ekstrand wrote:
> On Wed, Oct 14, 2015 at 1:41 AM, Pohjolainen, Topi
> wrote:
> > On Wed, Oct 14, 2015 at 11:25:40AM +0300, Pohjolainen, Topi wrote:
> >> On Sat, Oct 10, 2015 at 08:09:01AM -0700, Jason Ekstrand wrote:
> >
On Fri, Oct 09, 2015 at 05:50:22AM -0700, Jason Ekstrand wrote:
> On Fri, Oct 9, 2015 at 12:10 AM, Pohjolainen, Topi
> wrote:
> > On Thu, Oct 08, 2015 at 05:22:47PM -0700, Jason Ekstrand wrote:
> >> This commit moves the common/modern stuff. Some legacy stuff such as
>
On Thu, Oct 15, 2015 at 07:29:31AM -0700, Jason Ekstrand wrote:
>On Oct 14, 2015 10:48 PM, "Pohjolainen, Topi"
>wrote:
>>
>> On Wed, Oct 14, 2015 at 11:53:37AM -0700, Jason Ekstrand wrote:
>> > On Wed, Oct 14, 2015 at 1:41 AM, Pohjolainen
On Fri, Oct 16, 2015 at 08:24:11AM -0700, Jason Ekstrand wrote:
> On Fri, Oct 16, 2015 at 12:35 AM, Pohjolainen, Topi
> wrote:
> > On Fri, Oct 09, 2015 at 05:50:22AM -0700, Jason Ekstrand wrote:
> >> On Fri, Oct 9, 2015 at 12:10 AM, Pohjolainen, Topi
> >> wrote:
>
On Mon, Oct 19, 2015 at 02:29:04PM -0700, Anuj Phogat wrote:
> On Thu, Aug 13, 2015 at 2:51 PM, Anuj Phogat wrote:
> > Vertical alignment is not applicable to 1D textures.
> >
> > Signed-off-by: Anuj Phogat
> > ---
> > src/mesa/drivers/dri/i965/brw_tex_layout.c | 4 +++-
> > 1 file changed, 3 in
On Wed, Oct 21, 2015 at 03:58:12PM -0700, Matt Turner wrote:
> It was being memset to 0 previously.
> ---
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
> src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 2 +-
> src/mesa/drivers/dri/i965/intel_asm_annotation.c | 3 +++
> 3 files chan
On Wed, Oct 21, 2015 at 03:58:13PM -0700, Matt Turner wrote:
> Often annotations are identical between sets of consecutive
> instructions. We can perhaps avoid some memory allocations by reusing
> the previous annotation.
> ---
> src/mesa/drivers/dri/i965/intel_asm_annotation.c | 19 ++
On Wed, Oct 21, 2015 at 03:58:14PM -0700, Matt Turner wrote:
> Will allow annotations to contain error messages (indicating an
> instruction violates a rule for instance) that are printed after the
> disassembly of the block.
> ---
> src/mesa/drivers/dri/i965/intel_asm_annotation.c | 60
> +++
On Tue, Oct 27, 2015 at 01:18:42PM +0200, Tapani P?lli wrote:
> This makes sure that user is still able to query properties about
> variables that have gotten removed by opt_dead_builtin_varyings pass.
>
> Fixes following OpenGL ES 3.1 test:
>ES31-CTS.program_interface_query.output-layout
>
>
On Tue, Oct 27, 2015 at 10:28:58AM +0100, Iago Toral Quiroga wrote:
> We need this so we can configure different behaviors for passes that
> cannot deal with side-effectful instructions (CSE) and passes that can
> (we will add a load-combine pass shortly).
>
> For now, when allow_loads is true, we
On Wed, Oct 28, 2015 at 01:58:41AM -0700, Kenneth Graunke wrote:
> Consider the case of two nearly identical GLSL fragment shaders:
>
>out vec4 color;
>void main() { color = vec4(1); }
>
> and
>
>layout(early_fragment_tests) in;
>out vec4 color;
>void main() { color = vec4(1)
On Tue, Nov 10, 2015 at 06:33:44PM -0800, Kenneth Graunke wrote:
> A while back, we moved to directly emitting the Gen7+ state when
> constructing the binding tables. These flags are only used on
> Gen4-6, which emit all the binding table pointers at once.
>
> We gain nothing by having separate f
On Thu, Nov 12, 2015 at 03:38:51PM -0800, Kenneth Graunke wrote:
> I was going to add scalar_tcs and scalar_tes flags, and then thought
> better of it and decided to convert this to an array. Simpler.
>
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/brw_compiler.h |
On Thu, Nov 12, 2015 at 03:38:52PM -0800, Kenneth Graunke wrote:
> This was getting pretty out of hand, and with compute partially in place
> and tessellation on the way, it was only going to get worse.
>
> This patch makes a "stage exists?" predicate and a "number of stages"
> count and uses them
On Thu, Feb 05, 2015 at 10:23:27AM -0500, Ilia Mirkin wrote:
> Topi, this is awesome! I wanted to do something like that last night,
> but tiredness and laziness got in the way. Can I find these in git
> form somewhere so that I'll be able to integrate when doing a resend?
> (Also, I think it's fin
On Thu, Feb 05, 2015 at 10:39:31AM -0800, Matt Turner wrote:
> Maybe squash this somewhere? I'm not sure.
I felt silly leaving it alone but I didn't really have a good squash
candidate for it. Perhaps somebody comes up with an idea, or we can just
toss a coin :)
___
On Thu, Feb 05, 2015 at 11:56:33PM -0500, Ilia Mirkin wrote:
> From: Dave Airlie
>
> Signed-off-by: Dave Airlie
> Reviewed-by: Matt Turner
If we want to squash this somewhere, the first patch of the split
(glsl: Add double builtin type) could be a candidate - we get rid of
one warning.
> ---
On Fri, Feb 06, 2015 at 09:18:35AM +0200, Ian Romanick wrote:
> On 02/06/2015 06:56 AM, Ilia Mirkin wrote:
> > From: Dave Airlie
> >
> > This adds support for the new uniform interfaces
> > from ARB_gpu_shader_fp64.
> >
> > v2:
> > support ARB_separate_shader_objects ProgramUniform*d* (Ian)
> >
On Thu, Feb 05, 2015 at 11:56:28PM -0500, Ilia Mirkin wrote:
> From: Dave Airlie
>
> This causes a lot of warnings about unchecked type in
> switch statements - fix them later.
The rest of the series fixes things in the compiler frontend but leaves
a lot unchecked in the compiler backend (at lea
On Fri, Feb 06, 2015 at 10:04:13AM +0200, Pohjolainen, Topi wrote:
> On Thu, Feb 05, 2015 at 11:56:28PM -0500, Ilia Mirkin wrote:
> > From: Dave Airlie
> >
> > This causes a lot of warnings about unchecked type in
> > switch statements - fix them later.
>
> Th
On Tue, Feb 17, 2015 at 05:39:33PM -0800, Kenneth Graunke wrote:
> There's some debate about whether we should use Meta or BLORP,
> but either should run circles around the BLT engine.
>
> In particular, this means that Gen8+ will use the 3D engine for blits,
> like we do on Gen6-7.
>
> Improves
On Fri, Feb 27, 2015 at 12:06:00AM -0800, Kenneth Graunke wrote:
> This makes another part of the INTEL_DEBUG=shader_time code emittable
> at arbitrary locations, rather than just at the end of the instruction
> stream.
>
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/brw_fs.
On Fri, Feb 27, 2015 at 12:05:59AM -0800, Kenneth Graunke wrote:
> Instead of emit_shader_time_write, we now do emit(SHADER_TIME_ADD(...)).
> The advantage is that we can also insert a shader time write at an
> arbitrary location in the instruction stream, rather than being
> restricted to emitting
On Fri, Feb 27, 2015 at 12:06:01AM -0800, Kenneth Graunke wrote:
> Previously, we emitted the shader-time epilogue from emit_fb_writes(),
> during the middle of looping through color regions (or emit_urb_writes
> for the VS). This is duplicated several times and rather awkward.
>
> I need to fix
On Fri, Feb 27, 2015 at 11:15:35AM -0800, Kenneth Graunke wrote:
> This makes another part of the INTEL_DEBUG=shader_time code emittable
> at arbitrary locations, rather than just at the end of the instruction
> stream.
>
> v2: Don't lose smear! Caught by Topi Pohjolainen.
>
> Signed-off-by: Ken
On Tue, Mar 03, 2015 at 05:08:23PM +, Neil Roberts wrote:
> Jason Ekstrand writes:
>
> > On Mon, Mar 2, 2015 at 11:33 AM, Ilia Mirkin wrote:
> >
> >> On Mon, Mar 2, 2015 at 2:32 PM, Jason Ekstrand
> >> wrote:
> >> >
> >> >
> >> > On Mon, Mar 2, 2015 at 11:18 AM, Ilia Mirkin
> >> wrote:
> >
On Wed, Mar 04, 2015 at 08:44:19PM -0800, Kenneth Graunke wrote:
> A while back I switched intel_blit_framebuffer to prefer Meta over the
> BLT. This meant that Gen8 platforms would start using the 3D engine
> for blits, just like we do on Gen6-7.5.
>
> However, I hadn't considered Gen4-5 when ma
On Fri, Feb 27, 2015 at 05:34:44PM +0200, Francisco Jerez wrote:
> ---
> src/mesa/drivers/dri/i965/brw_eu.h | 19 ++--
> src/mesa/drivers/dri/i965/brw_eu_emit.c | 58
> ++--
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 55 +---
On Fri, Feb 27, 2015 at 05:34:45PM +0200, Francisco Jerez wrote:
> This was telling the sampler to do texture fetches for *all* channels
> in the non-constant surface index case, what could have reduced
> throughput unnecessarily when some of the channels were disabled by
> control flow.
> ---
> s
On Fri, Feb 27, 2015 at 05:34:47PM +0200, Francisco Jerez wrote:
> This is currently not a problem because the vec4 visitor happens to
> mask out unused components from the destination, but it might become
> an issue when we start using atomics without writeback message. In
> any case it seems sen
On Fri, Feb 27, 2015 at 05:34:49PM +0200, Francisco Jerez wrote:
> The generate_untyped_*() methods do nothing useful other than calling
> the corresponding function from brw_eu_emit.c. The calls to
> brw_mark_surface_used() will go away too in a future commit.
> ---
> src/mesa/drivers/dri/i965/b
On Fri, Feb 27, 2015 at 05:34:50PM +0200, Francisco Jerez wrote:
> ---
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
> src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 3 ++-
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
Reviewed-by: Topi Pohjolainen
__
On Fri, Feb 27, 2015 at 05:34:51PM +0200, Francisco Jerez wrote:
> This doesn't actually enable untyped surface message sends from GRF
> yet, the upcoming atomic counter and image intrinsic lowering code
> will.
> ---
> src/mesa/drivers/dri/i965/brw_vec4.cpp | 7 ---
> src/mesa/driv
On Fri, Feb 27, 2015 at 05:34:52PM +0200, Francisco Jerez wrote:
> ---
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 5 +++--
> src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +-
> src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 6 --
> src/mesa/drivers/dri/i965/brw_vec4_visito
On Fri, Feb 27, 2015 at 05:34:53PM +0200, Francisco Jerez wrote:
> This is consistent with the untyped surface read opcode. From now on
> all typed and untyped surface access opcodes will follow the same
> pattern: src[0] will be the message payload, src[1] will be the
> surface index and src[2] w
On Fri, Feb 27, 2015 at 05:34:46PM +0200, Francisco Jerez wrote:
> And calculate the message response size based on the number of
> components rather than the other way around. This simplifies their
> interface somewhat and allows the caller to request a writeback
> message with more than one vect
On Fri, Mar 06, 2015 at 10:37:06AM +0200, Pohjolainen, Topi wrote:
> On Fri, Feb 27, 2015 at 05:34:44PM +0200, Francisco Jerez wrote:
> > ---
> > src/mesa/drivers/dri/i965/brw_eu.h | 19 ++--
> > src/mesa/drivers/dri/i965/brw_eu
On Fri, Mar 06, 2015 at 01:33:05AM -0800, Kenneth Graunke wrote:
> On Gen8+, AND/OR/XOR/NOT don't support the abs() source modifier, and
> negate changes meaning to bitwise-not (~, not -). This isn't what NIR
> expects, so we should resolve the source modifers via a MOV.
>
> +30 Piglits (fs-op-bi
On Fri, Feb 27, 2015 at 05:34:48PM +0200, Francisco Jerez wrote:
> Change brw_untyped_atomic() and brw_untyped_surface_read() to take the
> surface index as a register instead of a constant and to use
> brw_send_indirect_message() to emit the indirect variant of send with
> a dynamically calculated
On Fri, Mar 06, 2015 at 02:29:15PM +0200, Francisco Jerez wrote:
> "Pohjolainen, Topi" writes:
>
> > On Fri, Feb 27, 2015 at 05:34:48PM +0200, Francisco Jerez wrote:
> >> Change brw_untyped_atomic() and brw_untyped_surface_read() to take the
> >> surface i
On Fri, Mar 06, 2015 at 02:46:51PM +0200, Francisco Jerez wrote:
> "Pohjolainen, Topi" writes:
>
> > On Fri, Mar 06, 2015 at 02:29:15PM +0200, Francisco Jerez wrote:
> >> "Pohjolainen, Topi" writes:
> >>
> >> > On Fri, Feb 27, 2
On Fri, Feb 27, 2015 at 05:34:44PM +0200, Francisco Jerez wrote:
> ---
> src/mesa/drivers/dri/i965/brw_eu.h | 19 ++--
> src/mesa/drivers/dri/i965/brw_eu_emit.c | 58
> ++--
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 55 +---
On Fri, Mar 06, 2015 at 03:11:27PM +0200, Francisco Jerez wrote:
> "Pohjolainen, Topi" writes:
>
> > On Fri, Feb 27, 2015 at 05:34:51PM +0200, Francisco Jerez wrote:
> >> This doesn't actually enable untyped surface message sends from GRF
> >> yet, th
On Sat, Mar 07, 2015 at 04:15:08PM +0200, Francisco Jerez wrote:
> Topi Pohjolainen writes:
>
> > The original patch from Curro was based on something that is not
> > present in the master yet. This patch tries to mimick the logic on
> > top master.
> > I wanted to see if could separate the build
On Mon, Mar 09, 2015 at 12:43:08PM +0200, Francisco Jerez wrote:
> "Pohjolainen, Topi" writes:
>
> > On Sat, Mar 07, 2015 at 04:15:08PM +0200, Francisco Jerez wrote:
> >> Topi Pohjolainen writes:
> >>
> >> > The original patch from Curro was
On Sun, Jan 29, 2017 at 08:24:16PM -0800, Kenneth Graunke wrote:
> ...and provide a better citation for the existing one.
>
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/brw_pipe_control.c | 32
> +---
> 1 file changed, 24 insertions(+), 8 deletions(
On Tue, Jan 31, 2017 at 06:13:45PM +0200, Topi Pohjolainen wrote:
> v2:
>- Fix return value (s/MESA_FORMAT_NONE/false/) (Anuj)
>- Move _mesa_tex_format_from_format_and_type() just
> in the end avoiding additional if-block (Anuj)
>- Explain better the array alignment restriction (An
On Tue, Jan 31, 2017 at 11:12:31AM -0800, Jason Ekstrand wrote:
>On Tue, Jan 31, 2017 at 10:38 AM, Jason Ekstrand
><[1]ja...@jlekstrand.net> wrote:
>
>On Tue, Jan 31, 2017 at 8:15 AM, Topi Pohjolainen
><[2]topi.pohjolai...@gmail.com> wrote:
>
> Current estimate doesn't consid
On Tue, Jan 31, 2017 at 01:37:25PM -0800, Jason Ekstrand wrote:
>On Wed, Jan 25, 2017 at 10:39 AM, Pohjolainen, Topi
><[1]topi.pohjolai...@gmail.com> wrote:
>
> On Mon, Jan 23, 2017 at 10:21:54PM -0800, Ben Widawsky wrote:
> > On Gen9 hardware, the d
On Tue, Jan 31, 2017 at 11:05:28AM -0800, Jason Ekstrand wrote:
> While we're at it, we rename it to remove the brw_ prefix
Nice! Both patches:
Reviewed-by: Topi Pohjolainen
>
> Signed-off-by: Jason Ekstrand
> ---
> src/intel/blorp/blorp.c | 26 +-
> src/intel/blorp/blo
On Sun, Feb 05, 2017 at 10:48:11PM -0800, Ben Widawsky wrote:
> On 17-01-25 20:53:44, Topi Pohjolainen Topi Pohjolainen wrote:
> > On Mon, Jan 23, 2017 at 10:21:43PM -0800, Ben Widawsky wrote:
> > > Make the code only disable CCS when it has to, unlike before where it
>
On Mon, Feb 13, 2017 at 01:25:57PM +0200, Lonnberg, Toni wrote:
> ---
> src/mesa/drivers/dri/i965/brw_disasm.c | 109
> +++--
> src/mesa/drivers/dri/i965/brw_inst.h | 31 +-
> 2 files changed, 135 insertions(+), 5 deletions(-)
>
> diff --git a/src/mesa/driv
On Fri, Feb 17, 2017 at 04:03:48PM -0800, Jason Ekstrand wrote:
> The isl_surf_init call that each of these helpers make can, in theory,
> fail. We should propagate that up to the caller rather than just
> silently ignoring it.
Reviewed-by: Topi Pohjolainen
> ---
> src/intel/isl/isl.c
On Fri, Feb 17, 2017 at 09:32:03PM +0200, Topi Pohjolainen wrote:
> Currently:
>
> 1) Blorp color clears and resolves emit unconditional render target
>flush + command stream after every clear/resolve (including
>regular non-fast clears).
>
> 2) Blorp color clears, resolves and blits emit
Sorry for the typo in the subject, this is version three.
On Tue, Feb 28, 2017 at 10:02:42AM +0200, Topi Pohjolainen wrote:
> Current estimate doesn't consider space needed for surface states
> and it only calculates for one shader stage. Each stage can have
> its own sampler and surface state co
On Tue, Jul 21, 2015 at 07:38:49PM +0300, Francisco Jerez wrote:
> v2: Move the image_params array back to brw_stage_prog_data.
> ---
> src/mesa/drivers/dri/i965/brw_shader.cpp | 31 +++
> src/mesa/drivers/dri/i965/brw_shader.h | 1 +
> 2 files changed, 32 insertions
On Wed, Aug 05, 2015 at 10:36:09AM +0300, Pohjolainen, Topi wrote:
> On Tue, Jul 21, 2015 at 07:38:49PM +0300, Francisco Jerez wrote:
> > v2: Move the image_params array back to brw_stage_prog_data.
> > ---
> > src/mesa/drivers/dri/i96
On Mon, Jul 20, 2015 at 07:17:48PM +0300, Francisco Jerez wrote:
> This will be used to pass image meta-data to the shader when we cannot
> use typed surface reads and writes. All entries except surface_idx
> and size are otherwise unused and will get eliminated by the uniform
> packing pass. siz
On Wed, Aug 05, 2015 at 12:11:02PM +0300, Pohjolainen, Topi wrote:
> On Mon, Jul 20, 2015 at 07:17:48PM +0300, Francisco Jerez wrote:
> > This will be used to pass image meta-data to the shader when we cannot
> > use typed surface reads and writes. All entries except surface_idx
&
On Mon, Jul 20, 2015 at 07:17:48PM +0300, Francisco Jerez wrote:
> This will be used to pass image meta-data to the shader when we cannot
> use typed surface reads and writes. All entries except surface_idx
> and size are otherwise unused and will get eliminated by the uniform
> packing pass. siz
On Wed, Aug 05, 2015 at 01:47:26PM +0300, Francisco Jerez wrote:
> "Pohjolainen, Topi" writes:
>
> > On Wed, Aug 05, 2015 at 10:36:09AM +0300, Pohjolainen, Topi wrote:
> >> On Tue, Jul 21, 2015 at 07:38:49PM +0300, Francisco Jerez wrote:
> >> &
On Wed, Aug 05, 2015 at 12:51:19PM +0300, Pohjolainen, Topi wrote:
> On Mon, Jul 20, 2015 at 07:17:48PM +0300, Francisco Jerez wrote:
> > This will be used to pass image meta-data to the shader when we cannot
> > use typed surface reads and writes. All entries except surface_idx
&
On Wed, Aug 05, 2015 at 12:11:02PM +0300, Pohjolainen, Topi wrote:
> On Mon, Jul 20, 2015 at 07:17:48PM +0300, Francisco Jerez wrote:
> > This will be used to pass image meta-data to the shader when we cannot
> > use typed surface reads and writes. All entries except surface_idx
&
On Mon, Jul 20, 2015 at 07:23:00PM +0300, Francisco Jerez wrote:
> v2: Add CS support.
> ---
> src/mesa/drivers/dri/i965/brw_cs.cpp | 3 ++-
> src/mesa/drivers/dri/i965/brw_gs.c | 1 +
> src/mesa/drivers/dri/i965/brw_vs.c | 3 ++-
> src/mesa/drivers/dri/i965/brw_wm.c | 3 ++-
> 4 files chang
On Mon, Jul 20, 2015 at 07:23:47PM +0300, Francisco Jerez wrote:
> v2: Add CS support. Move the image_params array back to
> brw_stage_prog_data.
Reviewed-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/brw_context.h | 10 +++-
> src/mesa/drivers/dri/i965/brw_gs_surface_sta
On Thu, Aug 13, 2015 at 08:00:43PM +0300, Martin Peres wrote:
> v2, Review from Francisco Jerez:
> - avoid the camelCase for the booleans
> - init the booleans using the sampler type
> - force the initialization of all the components of the output register
>
> Signed-off-by: Martin Peres
> ---
>
On Thu, Aug 13, 2015 at 07:58:53PM +0300, Martin Peres wrote:
> The code is heavily inspired from Francisco Jerez's code supporting the
> image_load_store extension.
>
> Backends willing to support this builtin should handle
> __intrinsic_image_size.
>
> v2: Based on the review of Ilia Mirkin
> -
On Thu, Aug 13, 2015 at 02:51:58PM -0700, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_tex_layout.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> b/src/mesa/drivers/dri/i965/
On Fri, Aug 14, 2015 at 04:51:52PM -0700, Anuj Phogat wrote:
> This change is required by the later patches.
>
> Cc: Ben Widawsky
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 ++-
> src/mesa/drivers/dri/i965/brw_misc_state.c| 8 +---
> src/mesa/
On Fri, Aug 14, 2015 at 03:30:18PM -0700, Connor Abbott wrote:
> In some cases, we need to emit ALU instructions with a certain stride
> due to a HW limitation. When splitting that instruction, we need to
> respect the original stride when creating the temporaries we load from
> and store into. Oth
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