Signed-off-by: Anuj Phogat
---
docs/features.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/features.txt b/docs/features.txt
index 85ad1a1..4c744c6 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -319,7 +319,7 @@ Khronos, ARB, and OES extensions that are
ceCount < instance->physicalDeviceCount) {
> + return VK_INCOMPLETE;
> } else {
>*pPhysicalDeviceCount = 0;
> }
> --
> 2.10.0
>
> ___
> mesa-dev mailing list
> mesa-d
}
> }
> +
> + sf.MultisampleRasterizationMode = (ms_info &&
> ms_info->rasterizationSamples > 1) ?
> + MSRASTMODE_ON_PATTERN :
> MSRASTMODE_OFF_PIXEL;
> #endif
>
> #if GEN_GEN >= 8
> --
> 2.8.1
>
> ___
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>
Both patches are:
Reviewed-by: Anuj Phogat
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This will help sharing multisample state setting code.
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/gen8_pipeline.c | 40 ---
src/intel/vulkan/genX_pipeline_util.h | 40 +++
2 files changed, 40 insertions(+), 40 deletions
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/gen7_pipeline.c | 16 +---
1 file changed, 1 insertion(+), 15 deletions(-)
diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c
index 5395e79..17d7ccc 100644
--- a/src/intel/vulkan/gen7_pipeline.c
+++ b/src
V1: Add multisample positions (Nanley)
V2: Fix 8x sample positions (Anuj)
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/genX_pipeline_util.h | 47 +++
1 file changed, 47 insertions(+)
diff --git a/src/intel/vulkan/genX_pipeline_util.h
b/src/intel/vulkan
Passes all 30 min_sample_shading tests in vulkan cts.
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/anv_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index c2c5153..b0b48ea 100644
--- a/src/intel
and
>
> On Mon, Aug 8, 2016 at 2:57 PM, Anuj Phogat wrote:
>>
>> Signed-off-by: Anuj Phogat
>> ---
>> src/intel/vulkan/gen7_pipeline.c | 16 +---
>> 1 file changed, 1 insertion(+), 15 deletions(-)
>>
>> diff --git a/src/intel/vulkan/
V1: Add multisample positions (Nanley)
V2: Fix 8x sample positions to match OpenGL (Anuj)
V3: Vulkan has standard sample locations. They need not be same as
in OpenGL. (Anuj)
Signed-off-by: Anuj Phogat
Reviewed-by: Jason Ekstrand
---
src/intel/vulkan/genX_pipeline_util.h | 47
Suggested-by: Jason Ekstrand
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/genX_multisample.h | 95 +++
src/intel/vulkan/genX_pipeline_util.h | 35 ++---
src/intel/vulkan/genX_state.c | 68 +++--
3 files changed, 106
patterns that have a
higher standard deviation but I think after some discussion it was
decided that it would be better to pick the same pattern as the other
graphics API in case there are games that rely on this pattern."
Observed no regressions in jenkins testing.
Signed-off-by: Anuj Phogat
Cc:
On Fri, Jul 29, 2016 at 2:30 PM, Anuj Phogat wrote:
>
>
> On Fri, Jul 29, 2016 at 12:32 PM, Anuj Phogat wrote:
>>
>>
>>
>> On Thu, Jul 28, 2016 at 6:31 PM, Jason Ekstrand
>> wrote:
>>>
>>> On Jul 28, 2016 7:37 PM, "Anuj Phoga
On Thu, Aug 11, 2016 at 10:53 AM, Jason Ekstrand wrote:
>
>
> On Thu, Aug 11, 2016 at 10:41 AM, Anuj Phogat wrote:
>>
>> There are no standard sample positions defined in OpenGL and OpenGL
>> ES specs. Implementations have the freedom to pick the positions
>>
This is required following the change in 8X sample positions.
Fixes the recently modified multisample-scaled-blit piglit tests.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 10 +-
src/mesa/drivers/dri/i965/gen6_multisample_state.c | 2 +-
2 files
patterns that have a
higher standard deviation but I think after some discussion it was
decided that it would be better to pick the same pattern as the other
graphics API in case there are games that rely on this pattern."
Observed no regressions in jenkins testing.
Signed-off-by: Anuj Phogat
Cc:
On Thu, Aug 11, 2016 at 4:06 PM, Jason Ekstrand wrote:
> Thanks!
>
> Reviewed-by: Jason Ekstrand
>
> On Thu, Aug 11, 2016 at 10:39 AM, Anuj Phogat wrote:
>>
>> Suggested-by: Jason Ekstrand
>> Signed-off-by: Anuj Phogat
>> ---
>>
's technically a regression between the two. Both
> are
>
> Reviewed-by: Jason Ekstrand
>
> On Thu, Aug 11, 2016 at 12:28 PM, Anuj Phogat wrote:
>>
>> This is required following the change in 8X sample positions.
>> Fixes the recently modified multisample-scal
>
> ___
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Thanks for fixing this.
Reviewed-by: Anuj Phogat
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It was holding the jenkins system to run cts on HSW. So I pushed
[PATCH 1/2] upstream.
On Fri, Aug 12, 2016 at 5:02 PM, Anuj Phogat wrote:
> On Thu, Aug 11, 2016 at 10:25 AM, Lionel Landwerlin
> wrote:
>> SampleMask is only 8bits long on gen7.
>>
>> Signed-off-by:
lGetTexImage()");
> + ctx->Driver.UnmapTextureImage(ctx, texImage, img);
> + return;
> + }
> }
> }
>
> --
> 1.9.1
>
> _______
> mesa-stable mailing list
> mesa-sta...@lists
Vulkan format");
> + assert(!"Unsupported Vulkan format");
>return 0;
> }
> }
> --
> Cheers,
> Eric
>
> ___
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> mesa-dev@list
_
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Series is:
Reviewed-by: Anuj Phogat
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On Tue, Aug 30, 2016 at 12:18 PM, Eric Engestrom wrote:
> On Tue, Aug 30, 2016 at 10:10:41AM -0700, Anuj Phogat wrote:
>> On Tue, Aug 30, 2016 at 3:36 AM, Eric Engestrom
>> wrote:
>> > Signed-off-by: Eric Engestrom
>> > ---
>> > src/intel/vulkan/anv_
TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
> - .dynamicStateCount = 9,
> - .pDynamicStates = (VkDynamicState[]) {
> -VK_DYNAMIC_STATE_VIEWPORT,
> -VK_DYNAMIC_STATE_SCISSOR,
> -VK_DYNAMIC_STATE_LINE_WIDTH,
> -VK_DYNAMIC_STATE_DEPTH_BIAS,
> -VK_DYNAMIC_STATE_BLEND_CONSTANTS,
> -VK_DYNAMIC_STATE_DEPTH_BOUNDS,
> -VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
> -VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
> -VK_DYNAMIC_STATE_STENCIL_REFERENCE,
> - },
> - },
> - .flags = 0,
> - .layout = device->meta_state.blit.pipeline_layout,
> - .renderPass = device->meta_state.blit.render_pass,
> - .subpass = 0,
> - };
> -
> - const struct anv_graphics_pipeline_create_info anv_pipeline_info = {
> - .color_attachment_count = -1,
> - .use_repclear = false,
> - .disable_vs = true,
> - .use_rectlist = true
> - };
> -
> - pipeline_shader_stages[1].module = anv_shader_module_to_handle(&fs_1d);
> - result = anv_graphics_pipeline_create(anv_device_to_handle(device),
> - VK_NULL_HANDLE,
> - &vk_pipeline_info, &anv_pipeline_info,
> - &device->meta_state.alloc, &device->meta_state.blit.pipeline_1d_src);
> - if (result != VK_SUCCESS)
> - goto fail_pipeline_layout;
> -
> - pipeline_shader_stages[1].module = anv_shader_module_to_handle(&fs_2d);
> - result = anv_graphics_pipeline_create(anv_device_to_handle(device),
> - VK_NULL_HANDLE,
> - &vk_pipeline_info, &anv_pipeline_info,
> - &device->meta_state.alloc, &device->meta_state.blit.pipeline_2d_src);
> - if (result != VK_SUCCESS)
> - goto fail_pipeline_1d;
> -
> - pipeline_shader_stages[1].module = anv_shader_module_to_handle(&fs_3d);
> - result = anv_graphics_pipeline_create(anv_device_to_handle(device),
> - VK_NULL_HANDLE,
> - &vk_pipeline_info, &anv_pipeline_info,
> - &device->meta_state.alloc, &device->meta_state.blit.pipeline_3d_src);
> - if (result != VK_SUCCESS)
> - goto fail_pipeline_2d;
> -
> - ralloc_free(vs.nir);
> - ralloc_free(fs_1d.nir);
> - ralloc_free(fs_2d.nir);
> - ralloc_free(fs_3d.nir);
> -
> - return VK_SUCCESS;
> -
> - fail_pipeline_2d:
> - anv_DestroyPipeline(anv_device_to_handle(device),
> - device->meta_state.blit.pipeline_2d_src,
> - &device->meta_state.alloc);
> -
> - fail_pipeline_1d:
> - anv_DestroyPipeline(anv_device_to_handle(device),
> - device->meta_state.blit.pipeline_1d_src,
> - &device->meta_state.alloc);
> -
> - fail_pipeline_layout:
> - anv_DestroyPipelineLayout(anv_device_to_handle(device),
> - device->meta_state.blit.pipeline_layout,
> - &device->meta_state.alloc);
> - fail_descriptor_set_layout:
> - anv_DestroyDescriptorSetLayout(anv_device_to_handle(device),
> - device->meta_state.blit.ds_layout,
> - &device->meta_state.alloc);
> - fail_render_pass:
> - anv_DestroyRenderPass(anv_device_to_handle(device),
> - device->meta_state.blit.render_pass,
> - &device->meta_state.alloc);
> -
> - ralloc_free(vs.nir);
> - ralloc_free(fs_1d.nir);
> - ralloc_free(fs_2d.nir);
> - ralloc_free(fs_3d.nir);
> - fail:
> - return result;
> -}
> --
> 2.5.0.400.gff86faf
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Patches 25-26 are:
Reviewed-by: Anuj Phogat
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On Wed, Aug 31, 2016 at 2:22 PM, Jason Ekstrand wrote:
> ---
> src/intel/vulkan/Makefile.sources | 1 -
> src/intel/vulkan/anv_blorp.c | 184
> ++
> src/intel/vulkan/anv_meta_copy.c | 180 -
> 3 files changed, 184 in
el),
> - .height = anv_minify(dest_image->extent.height,
> -region->dstSubresource.mipLevel),
> - .layers = 1
> -},
> -&cmd_buffer->pool->alloc,
> -&fb_h);
> -
> - ANV_CALL(CmdBeginR
On Sat, Sep 3, 2016 at 8:53 AM, Jason Ekstrand wrote:
>
>
> On Fri, Sep 2, 2016 at 12:05 PM, Anuj Phogat wrote:
>>
>> On Wed, Aug 31, 2016 at 2:22 PM, Jason Ekstrand
>> wrote:
>> > ---
>> > src/intel/vulkan/Makefile.sources | 1 -
unreachable("Unexpected target");
> }
>
> /* Guess a reasonable value for lastLevel. This is probably going
> --
> 2.7.4
>
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LGTM. I assume you've tested the patch for any regressions in
piglit and GL CTS.
Reviewed-by: Anuj Phogat
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emit(GS_OPCODE_GET_INSTANCE_ID, *reg);
> + else
> + emit(MOV(*reg, brw_imm_ud(0)));
>break;
> default:
>unreachable("not reached");
> --
> 2.10.0
>
> ___
e base address for the primary after
> +* all of the secondaries are done.
> +*
> +* TODO: Maybe we want to make this a dirty bit to avoid extra state base
> +* address calls?
> +*/
> + anv_cmd_buffer_emit_state_base_address(primary);
> }
>
gt; .swap_buffers_region = dri2_fallback_swap_buffers_region,
> .post_sub_buffer = dri2_fallback_post_sub_buffer,
> --
> 2.10.0
>
> _______
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> https://lists.freedesktop.org/mailman/listinfo/mesa-de
No functional changes in this patch.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/gen8_blend_state.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_blend_state.c
b/src/mesa/drivers/dri/i965/gen8_blend_state.c
index
No functional changes in this patch.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/gen8_blend_state.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_blend_state.c
b/src/mesa/drivers/dri/i965/gen8_blend_state.c
index 8aca8b8
We follow this rule at multiple places in i965 driver. This patch
doesn't fix any testcase.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/gen8_blend_state.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri
ormat_version": "1.0.0",
> "ICD": {
> "library_path": "libvulkan_radeon.so",
> -"abi_versions": "1.0.3"
> + "api_version": "1.0.3"
> }
> }
> --
> 2.7.3
>
> ___
a expected 0xc"
This patch fixes the GPU hang as well as the simulator warning with
new piglit test fbo-mrt-alphatest-no-buffer-zero-write:
https://patchwork.freedesktop.org/patch/118212
No regressions in Jenkins CI system.
Cc: "12.0 13.0"
Signed-off-by: Anuj Phogat
---
Signed-off-by: Anuj Phogat
---
src/mesa/main/framebuffer.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index 46a6f64..e1505fa 100644
--- a/src/mesa/main/framebuffer.c
+++ b/src/mesa/main/framebuffer.c
@@ -994,7
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_wm.c | 4 ++--
src/mesa/drivers/dri/i965/gen6_wm_state.c| 5 +++--
src/mesa/drivers/dri/i965/gen7_wm_state.c| 5 +++--
src/mesa/drivers/dri/i965/gen8_depth_state.c | 4 ++--
4 files changed, 10 insertions(+), 8
Signed-off-by: Anuj Phogat
---
src/mesa/main/framebuffer.c | 9 +
src/mesa/main/framebuffer.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index f19f3af..3aff102 100644
--- a/src/mesa/main/framebuffer.c
+++ b/src/mesa
Signed-off-by: Anuj Phogat
---
src/mesa/main/framebuffer.c | 7 +++
src/mesa/main/framebuffer.h | 3 +++
2 files changed, 10 insertions(+)
diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index e1505fa..f19f3af 100644
--- a/src/mesa/main/framebuffer.c
+++ b/src/mesa
On Tue, Oct 25, 2016 at 5:14 PM, Brian Paul wrote:
> On 10/25/2016 04:09 PM, Anuj Phogat wrote:
>>
>> Signed-off-by: Anuj Phogat
>> ---
>> src/mesa/main/framebuffer.c | 7 +++
>> src/mesa/main/framebuffer.h | 3 +++
>> 2 files changed, 10 inserti
On Tue, Oct 25, 2016 at 4:36 PM, Ilia Mirkin wrote:
> On Tue, Oct 25, 2016 at 7:09 PM, Anuj Phogat wrote:
>> Signed-off-by: Anuj Phogat
>> ---
>> src/mesa/drivers/dri/i965/brw_wm.c | 4 ++--
>> src/mesa/drivers/dri/i965/gen6_wm_state.c| 5 +++--
&g
dstib;
>
> GLuint *translated_elt_buf;
> @@ -104,7 +104,7 @@ struct copy_context {
> };
>
>
> -static GLuint attr_size( const struct gl_client_array *array )
> +static GLuint attr_size( const struct gl_vertex_array *array )
> {
> return array->Size * _mesa
; + }
> + OUT_BATCH(0x); /* white, but only alpha gets written */
> + ADVANCE_BATCH_TILED(dst_y_tiled, false);
> + }
> }
> - OUT_BATCH(0x); /* white, but only alpha gets written */
> - ADVANCE_BATCH_TILED(dst_y_tiled, false);
>
> brw_emit_mi_flush(brw);
> }
> --
> 2.5.0.400.gff86faf
>
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g_rect,
>
> @@ -251,7 +249,6 @@ static const struct brw_tracked_state
> *gen7_render_atoms[] =
> &brw_polygon_stipple_offset,
>
> &brw_line_stipple,
> - &brw_aa_line_parameters,
>
> &brw_drawing_rect,
>
> @@ -360,7 +357,6 @@ static const str
> - OUT_BATCH(0);
> - OUT_BATCH(0);
> - OUT_BATCH(0);
> - OUT_BATCH(0);
> - ADVANCE_BATCH();
> -
> - BEGIN_BATCH(2);
> - OUT_BATCH(_3DSTATE_WM_CHROMAKEY << 16 | (2 - 2));
> - OUT_BATCH(0);
> - ADVANCE_BATCH();
> -}
> -
> -const struct brw_tracked_state gen8_disable_stages = {
> - .di
p[4];
> - handle_trace_block(spec, p);
>break;
> default:
>break;
> --
> 2.9.3
>
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> https://lists.fre
t; - "execbuf2 failed: %m");
> + return vk_errorf(VK_ERROR_DEVICE_LOST, "execbuf2 failed: %m");
>}
> }
>
> --
> 2.5.0.400.gff86faf
>
> ___
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pect to the value expected by the GL, so we need to give it
> the same treatment as gl_FragCoord. Fixes the following CTS tests on
> i965:
Makes sense.
Reviewed-by: Anuj Phogat
>
>
> ES31-CTS.functional.shaders.multisample_interpolation.interpolate_at_offset.at_sample_positio
struct gl_program_constants *prog = &ctx->Const.Program[i];
> --
> 2.10.2
>
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Both patches are:
Reviewed-by: Anuj Phogat
On Tue, Nov 8, 2016 at 1:21 PM, Jason Ekstrand wrote:
> The precision of our trig instructions instructions appears to have been
>
s/instructions instructions/instructions
> fixed on Kaby Lake. Neither Ben nor I can find any documentation for this.
> However, the dEQP precision tests now pass
> Intel-gfx mailing list
> intel-...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
IDs cross checked in graphics specs.
Reviewed-by: Anuj Phogat
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Intel(R) Kabylake GT2")
>> CHIPSET(0x591B, kbl_gt2, "Intel(R) Kabylake GT2")
>> CHIPSET(0x591D, kbl_gt2, "Intel(R) Kabylake GT2")
>> --
>> 2.10.2
>>
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> + const bool depth_writes_enabled = brw_depth_writes_enabled(brw);
>
> /* _NEW_STENCIL:
> * !DEPTH_STENCIL_STATE::Stencil Buffer Write Enable ||
> diff --git a/src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c
> b/src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c
&
urrentProgram[MESA_SHADER_COMPUTE],
> cp, &key);
>(void) success;
>assert(success);
> --
> 2.10.2
>
> ___
> mesa-stable mailing list
> mesa-sta...@l
awFb, NULL);
> - _mesa_meta_end(ctx);
> -
> -cleanup:
> - _mesa_DeleteTextures(1, &src_view_texture);
> -
> - /* If we got a renderbuffer source, delete the temporary texture */
> - if (src_renderbuffer && src_tex_image)
> - ctx->Driver.DeleteTexture(ctx, src_tex_image->TexObject);
> -
> - return success;
> -}
> diff --git a/src/mesa/drivers/dri/i965/intel_copy_image.c
> b/src/mesa/drivers/dri/i965/intel_copy_image.c
> index 56eaed6..85585c7 100644
> --- a/src/mesa/drivers/dri/i965/intel_copy_image.c
> +++ b/src/mesa/drivers/dri/i965/intel_copy_image.c
> @@ -183,16 +183,6 @@ intel_copy_image_sub_data(struct gl_context *ctx,
> struct intel_mipmap_tree *src_mt, *dst_mt;
> unsigned src_level, dst_level;
>
> - if (brw->gen < 6 &&
> - _mesa_meta_CopyImageSubData_uncompressed(ctx,
> -src_image, src_renderbuffer,
> -src_x, src_y, src_z,
> -dst_image, dst_renderbuffer,
> -dst_x, dst_y, dst_z,
> -src_width, src_height)) {
> - return;
> - }
> -
> if (src_image) {
>src_mt = intel_texture_image(src_image)->mt;
>src_level = src_image->Level + src_image->TexObject->MinLevel;
> --
> 2.5.0.400.gff86faf
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Series is:
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S_URB_ENTRY_SIZE_BYTES;
> if (compiler->devinfo->gen == 6)
>max_output_size_bytes = GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES;
> --
> 2.10.2
>
> ___
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> https://lists.freedesktop
On Tue, Dec 6, 2016 at 10:58 AM, Alejandro Piñeiro wrote:
> The FIXME suggest that the check should be removed.
>
Only if we see any performance or feature benefits in doing that.
Last I checked I didn't see any performance benefits on Skylake.
I also couldn't figure out the cause of random failur
On Tue, Dec 6, 2016 at 4:26 PM, Anuj Phogat wrote:
> On Tue, Dec 6, 2016 at 10:58 AM, Alejandro Piñeiro
> wrote:
>> The FIXME suggest that the check should be removed.
>>
> Only if we see any performance or feature benefits in doing that.
> Last I checked I didn't
On Wed, Dec 7, 2016 at 3:38 AM, Alejandro Piñeiro wrote:
>
>
> On 07/12/16 09:36, Alejandro Piñeiro wrote:
>> On 06/12/16 22:26, Anuj Phogat wrote:
>>> On Tue, Dec 6, 2016 at 10:58 AM, Alejandro Piñeiro
>>> wrote:
>>>> The FIXME suggest that the che
ailing list
> mesa-sta...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-stable
For both patches:
Reviewed-by: Anuj Phogat
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t; ___
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On Tue, Dec 20, 2016 at 6:45 AM, Topi Pohjolainen
wrote:
>
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/intel_tex_image.c| 24 +++-
> src/mesa/drivers/dri/i965/intel_tex_subimage.c | 19 +--
> 2 files changed, 12 insertions(+), 31 de
>
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Patches 1-3 are:
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;
> +
> extern bool
> _mesa_is_es3_color_renderable(GLenum internal_format);
>
> --
> 2.5.5
>
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Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 27dfb0c..c557137 100644
--- a/src/mesa/drivers/dri/i965
Signed-off-by: Anuj Phogat
---
docs/GL3.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index ce34869..883604a 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -255,6 +255,7 @@ GLES3.2, GLSL ES 3.2
GL_KHR_debug DONE
Signed-off-by: Anuj Phogat
---
src/mapi/glapi/registry/gl.xml | 1 +
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/mtypes.h | 1 +
src/mesa/main/teximage.c | 5 +++--
4 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/mapi/glapi/registry/gl.xml b/src
On Fri, Jul 8, 2016 at 3:42 PM, Ilia Mirkin wrote:
> Signed-off-by: Ilia Mirkin
> Cc: "11.2 12.0"
> ---
>
> This is sort of pending a question to KHR at
>
> https://www.khronos.org/bugzilla/show_bug.cgi?id=1511
>
> but OTOH, no matter their answer, mesa doesn't have online compression for
> etc
teximage_only_format(ctx, format);
> }
>
> --
> 2.7.3
>
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V2: Drop the changes to gl.xml.
Signed-off-by: Anuj Phogat
---
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/mtypes.h | 1 +
src/mesa/main/teximage.c | 5 +++--
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/extensions_table.h b/src/mesa
On Thu, Jul 14, 2016 at 11:30 AM, Nanley Chery wrote:
> On Thu, Jul 14, 2016 at 11:12:45AM -0700, Anuj Phogat wrote:
>> V2: Drop the changes to gl.xml.
>>
>> Signed-off-by: Anuj Phogat
>> ---
>> src/mesa/main/extensions_table.h | 1 +
>> src/mesa/main/mty
On Fri, Jul 15, 2016 at 10:14 AM, Brian Paul wrote:
> If numSamples > 0, we can compute the size of the whole mipmapped texture.
> That's the case for glTexStorage(GL_PROXY_TEXTURE_x).
>
> Also, multiply the texture size by numSamples for MSAA textures.
> ---
> src/mesa/main/teximage.c | 48
> ++
On Fri, Jul 15, 2016 at 12:34 PM, Brian Paul wrote:
> On 07/15/2016 01:19 PM, Anuj Phogat wrote:
>>
>> On Fri, Jul 15, 2016 at 10:14 AM, Brian Paul wrote:
>>>
>>> If numSamples > 0, we can compute the size of the whole mipmapped
>>>
lacement->dest.ssa));
> } else {
> nir_dest_copy(&replacement->dest, &intrin->dest, state->mem_ctx);
> }
>}
>
>nir_instr_insert_before(&intrin->instr, &replacement->instr);
>nir_instr_remove(&am
+ _mesa_unlock_texture(ctx, texObj);
> + return;
> + }
> +
> if (target == GL_TEXTURE_CUBE_MAP) {
>GLuint face;
>for (face = 0; face < 6; face++) {
> --
> 2.9.0
>
> ___
> me
_
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= mt->logical_depth0 - layer,
> .channel_select = {
> swizzle_to_scs(GET_SWZ(surface->swizzle, 0)),
> swizzle_to_scs(GET_SWZ(surface->swizzle, 1)),
> --
> 2.5.0.400.gff86faf
>
> ___
>
On Thu, Jul 21, 2016 at 9:21 PM, Jason Ekstrand wrote:
> Signed-off-by: Jason Ekstrand
> Cc: "12.0"
> Cc: Nanley Chery
> ---
> src/intel/vulkan/anv_meta_clear.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/vulkan/anv_meta_clear.c
> b/src/intel/vulka
_FILE);
> +
It'll be nice to add this assert here:
assert(!prog_data->dual_src_blend || key->nr_color_regions == 1);
> if (inst == NULL) {
>/* Even if there's no color buffers enabled, we still need to send
> * alpha out the pipeline to our null renderbuffer to support
> @@ -914,7
Fixes ~45 DEQP sample shading tests:
./deqp-vk --deqp-case=dEQP-VK.pipeline.multisample.min_sample_shading*
Many tests exited with VK_ERROR_OUT_OF_DEVICE_MEMORY without this patch.
Cc: Jason Ekstrand
Signed-off-by: Anuj Phogat
---
Another patch enabling the sample shading is required to test
On Tue, Jul 26, 2016 at 7:27 PM, Jason Ekstrand
wrote:
> On Jul 26, 2016 12:54 PM, "Anuj Phogat" wrote:
> >
> > Fixes ~45 DEQP sample shading tests:
> > ./deqp-vk --deqp-case=dEQP-VK.pipeline.multisample.min_sample_shading*
> >
> > Many tests exited
Vulkan CTS test results on gen9:
./deqp-vk --deqp-case=dEQP-VK.pipeline.multisample.min_sample_shading*
Test run totals:
Passed:60/90 (66.7%)
Failed:0/90 (0.0%)
Not supported: 30/90 (33.3%)
Warnings: 0/90 (0.0%)
Cc: Jason Ekstrand
Signed-off-by: Anuj Phogat
---
src
We should use the persample_dispatch variable in prog_data.
Fixes all (~60) the DEQP sample shading tests. Many tests exited with
VK_ERROR_OUT_OF_DEVICE_MEMORY without this patch.
V2: Use the shader key bits set in brw_compile_fs (Jason)
Cc: Jason Ekstrand
Signed-off-by: Anuj Phogat
---
src
sampling.
I'll add sample shading bits after that.
> Reviewed-by: Jason Ekstrand
>
> On Jul 28, 2016 1:31 PM, "Anuj Phogat" wrote:
>
>> We should use the persample_dispatch variable in prog_data.
>>
>> Fixes all (~60) the DEQP sample shading tes
Fixes the vulkan cts regression in test dEQP-VK.api.info.device.properties
Cc: Mark Janes
Cc: Jason Ekstrand
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/anv_device.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan
On Thu, Jul 28, 2016 at 6:31 PM, Jason Ekstrand
wrote:
> On Jul 28, 2016 7:37 PM, "Anuj Phogat" wrote:
> >
> > Fixes the vulkan cts regression in test
> dEQP-VK.api.info.device.properties
> >
> > Cc: Mark Janes
> > Cc: Jason Ekstrand
> >
On Fri, Jul 29, 2016 at 12:32 PM, Anuj Phogat wrote:
>
>
> On Thu, Jul 28, 2016 at 6:31 PM, Jason Ekstrand
> wrote:
>
>> On Jul 28, 2016 7:37 PM, "Anuj Phogat" wrote:
>> >
>> > Fixes the vulkan cts regression in test
>> dEQP-VK.api.i
On Fri, Aug 5, 2016 at 10:05 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:
> Fixes 6 failures from dEQP-VK.api.copy_and_blit.resolve_image.*
>
No tests are run with --deqp-case=dEQP-VK.api.copy_and_blit.resolve_image.*
This is what i'm seeing on hsw without this patch:
./deqp-vk
On Fri, Aug 5, 2016 at 1:23 PM, Anuj Phogat wrote:
>
> On Fri, Aug 5, 2016 at 10:05 AM, Lionel Landwerlin <
> lionel.g.landwer...@intel.com> wrote:
>
>> Fixes 6 failures from dEQP-VK.api.copy_and_blit.resolve_image.*
>>
> No tests are run wi
f13b15d
. You should remove them from commit message if they are no longer
part of CTS.
> Tested on IVB/HSW
>
> v2: Check pMultisampleState is not NULL
>
> Signed-off-by: Lionel Landwerlin
> Cc: Anuj Phogat
> ---
> src/intel/vulkan/gen7_pipeline.c | 24
On Fri, Aug 5, 2016 at 4:38 PM, Jason Ekstrand wrote:
>
>
> On Fri, Aug 5, 2016 at 4:29 PM, Anuj Phogat wrote:
>
>>
>>
>> On Fri, Aug 5, 2016 at 3:57 PM, Lionel Landwerlin
>> wrote:
>>
>>> Fixes the following failures :
>>>
>
hes can also be found at my github branch:
https://github.com/aphogat/mesa.git branch: sample-shading-5
Anuj Phogat (8):
mesa: Add infrastructure for GL_ARB_sample_shading
mesa: Add new functions and enums required by GL_ARB_sample_shading
mesa: Pass number of samples as a program state variable
This patch implements the common support code required for the
GL_ARB_sample_shading extension.
Signed-off-by: Anuj Phogat
---
src/glsl/glcpp/glcpp-parse.y| 3 +++
src/glsl/glsl_parser_extras.cpp | 1 +
src/glsl/glsl_parser_extras.h | 2 ++
src/glsl/standalone_scaffolding.cpp
Number of samples will be required in fragment shader program by new
GLSL builtin uniform "gl_NumSamples".
Signed-off-by: Anuj Phogat
---
src/mesa/program/prog_statevars.c | 11 +++
src/mesa/program/prog_statevars.h | 2 ++
2 files changed, 13 insertions(+)
diff --git
New functions added by GL_ARB_sample_shading:
glMinSampleShadingARB()
New enums:
GL_SAMPLE_SHADING_ARB
GL_MIN_SAMPLE_SHADING_VALUE_ARB
Signed-off-by: Anuj Phogat
---
src/mapi/glapi/gen/ARB_sample_shading.xml | 19 +++
src/mapi/glapi/gen/GL3x.xml | 5 +
src
New builtins added by GL_ARB_sample_shading:
in vec2 gl_SamplePosition
in int gl_SampleID
in int gl_NumSamples
out int gl_SampleMask[]
Signed-off-by: Anuj Phogat
---
src/glsl/builtin_variables.cpp | 11 +++
src/glsl/link_varyings.cpp | 2 ++
src/mesa/main/mtypes.h | 7
Implement the FS backend for new builtins added by the extension:
in vec2 gl_SamplePosition
in int gl_SampleID
in int gl_NumSamples
out int gl_SampleMask[]
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 109 +++
src/mesa/drivers/dri/i965
- Enable GEN6_WM_MSDISPMODE_PERSAMPLE, GEN6_WM_POSOFFSET_SAMPLE,
GEN6_WM_OMASK_TO_RENDER_TARGET as per extension's specification.
- Don't enable GEN6_WM_16_DISPATCH_ENABLE when GEN6_WM_MSDISPMODE_PERSAMPLE
is enabled. Refer SNB PRM Vol. 2, Part 1, Page 279 for details.
Signed-of
- Enable GEN7_WM_MSDISPMODE_PERSAMPLE, GEN7_WM_POSOFFSET_SAMPLE,
GEN7_WM_OMASK_TO_RENDER_TARGET as per extension's specification.
- Don't enable GEN7_WM_16_DISPATCH_ENABLE when GEN7_WM_MSDISPMODE_PERSAMPLE
is enabled. Refer IVB PRM Vol. 2, Part 1, Page 288 for details.
Signed-of
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