Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.78 -> 1.79
---
Log message:
remove some unused instructions
---
Diffs of the changes: (+0 -12)
SparcV8InstrInfo.td | 12
1 files changed, 12 deletions(-)
Index: llvm/lib/Target/SparcV8/SparcV8Inst
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.16 -> 1.17
---
Log message:
V8 doesn't have FP extload
---
Diffs of the changes: (+2 -0)
SparcV8ISelDAGToDAG.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.15 -> 1.16
---
Log message:
simplifications, fix typo
---
Diffs of the changes: (+5 -6)
SparcV8ISelDAGToDAG.cpp | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/Spa
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.29 -> 1.30
---
Log message:
add a node, for completeness
---
Diffs of the changes: (+2 -0)
TargetSelectionDAG.td |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/li
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.14 -> 1.15
SparcV8InstrInfo.td updated: 1.77 -> 1.78
---
Log message:
Add frameindex support
Add support for copying (e.g. returning) doubles
Add support for F<->I instructions
---
Diffs of the changes: (+96 -26
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.cpp updated: 1.8 -> 1.9
---
Log message:
Tighten up some checks
---
Diffs of the changes: (+1 -5)
SparcV8InstrInfo.cpp |6 +-
1 files changed, 1 insertion(+), 5 deletions(-)
Index: llvm/lib/Target/SparcV8/SparcV8Instr
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.49 -> 1.50
---
Log message:
Fix a bug Sabre was having where the DAG root was a group. The group dominator
needed to be added to the ordering list, not the first member of the group.
---
Diffs of the changes: (+6
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.48 -> 1.49
---
Log message:
Groups were not emitted if the dominator node and the node in the ordering list
were not the same node. Ultimately the test was bogus.
---
Diffs of the changes: (+6 -10)
ScheduleDAG
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.28 -> 1.29
---
Log message:
Since extload can also be used by FP, split STDIntExtLoad into two parts,
one for use with extload, one for use with sextload and zextload, which
are integer only.
---
Diffs of the changes: (+5
Changes in directory llvm/lib/Target/SparcV8:
SparcV8AsmPrinter.cpp updated: 1.46 -> 1.47
SparcV8ISelDAGToDAG.cpp updated: 1.13 -> 1.14
SparcV8InstrInfo.td updated: 1.76 -> 1.77
---
Log message:
Add constant pool support, including folding into addresses.
Pretty print addresses a bit, to not pr
Changes in directory llvm/lib/Target/SparcV8:
SparcV8AsmPrinter.cpp updated: 1.45 -> 1.46
SparcV8ISelDAGToDAG.cpp updated: 1.12 -> 1.13
---
Log message:
Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes,
allowing us to compile this:
to this:
%G1 = external global int
%G
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.11 -> 1.12
SparcV8InstrInfo.td updated: 1.75 -> 1.76
---
Log message:
Add initial support for global variables, and fix a bug in addr mode selection
where we didn't select the operands.
---
Diffs of the changes:
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.74 -> 1.75
---
Log message:
Claiming that branch targets are registers is not very wholesome. Change them
to be basic blocks. Also, add uncond branches.
---
Diffs of the changes: (+56 -51)
SparcV8InstrInfo.td |
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.73 -> 1.74
---
Log message:
Add unordered comparisons
---
Diffs of the changes: (+8 -13)
SparcV8InstrInfo.td | 21 -
1 files changed, 8 insertions(+), 13 deletions(-)
Index: llvm/lib/Target
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.72 -> 1.73
---
Log message:
Add patterns to the rest of the int condbranches and some of the fp branches
---
Diffs of the changes: (+46 -23)
SparcV8InstrInfo.td | 69 ++---
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.10 -> 1.11
SparcV8InstrFormats.td updated: 1.13 -> 1.14
SparcV8InstrInfo.td updated: 1.71 -> 1.72
SparcV8RegisterInfo.td updated: 1.24 -> 1.25
---
Log message:
Add initial conditional branch support. This doesn't
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.47 -> 1.48
---
Log message:
Simplify code
---
Diffs of the changes: (+2 -7)
ScheduleDAG.cpp |9 ++---
1 files changed, 2 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.c
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.70 -> 1.71
SparcV8ISelSimple.cpp updated: 1.94 -> 1.95
---
Log message:
Eliminate CMPri, which is a synonym for SUBCCri
---
Diffs of the changes: (+3 -8)
SparcV8ISelSimple.cpp |2 +-
SparcV8InstrInfo.td |
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.230 -> 1.231
---
Log message:
allow custom expansion of BR_CC
---
Diffs of the changes: (+25 -11)
LegalizeDAG.cpp | 36 +---
1 files changed, 25 insertions(+), 11 deletions(-)
Changes in directory llvm/lib/Target/SparcV8:
README.txt updated: 1.39 -> 1.40
SparcV8InstrInfo.td updated: 1.69 -> 1.70
---
Log message:
add fneg,fabs,fsqrt instructions
---
Diffs of the changes: (+17 -5)
README.txt |4 +---
SparcV8InstrInfo.td | 18 --
2 fi
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.68 -> 1.69
---
Log message:
Add patterns for fround/fextend and the funny fsmuld instruction
---
Diffs of the changes: (+8 -4)
SparcV8InstrInfo.td | 12
1 files changed, 8 insertions(+), 4 deletions
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.67 -> 1.68
---
Log message:
Add FP +,-,*,/
---
Diffs of the changes: (+16 -8)
SparcV8InstrInfo.td | 24
1 files changed, 16 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/SparcV8
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrFormats.td updated: 1.12 -> 1.13
SparcV8InstrInfo.td updated: 1.66 -> 1.67
---
Log message:
Give patterns to F3_3 instructions
---
Diffs of the changes: (+22 -21)
SparcV8InstrFormats.td |3 ++-
SparcV8InstrInfo.td| 40
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.9 -> 1.10
---
Log message:
Implement 64-bit add/sub, make sure to receive and return 64-bit args with
the right halves in the right regs
---
Diffs of the changes: (+32 -4)
SparcV8ISelDAGToDAG.cpp | 36 ++
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.8 -> 1.9
---
Log message:
implement div and rem
---
Diffs of the changes: (+26 -0)
SparcV8ISelDAGToDAG.cpp | 26 ++
1 files changed, 26 insertions(+)
Index: llvm/lib/Target/SparcV8/
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.7 -> 1.8
---
Log message:
implement MULHU/MULHS for 64-bit multiplies
---
Diffs of the changes: (+11 -0)
SparcV8ISelDAGToDAG.cpp | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/lib/Target/S
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelSimple.cpp updated: 1.93 -> 1.94
SparcV8InstrInfo.td updated: 1.65 -> 1.66
SparcV8RegisterInfo.td updated: 1.23 -> 1.24
---
Log message:
Add patterns for multiply, simplify Y register handling stuff, add RDY
instruction
---
Diffs of th
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.6 -> 1.7
SparcV8InstrInfo.td updated: 1.64 -> 1.65
---
Log message:
Make the addressing modes smarter
---
Diffs of the changes: (+21 -10)
SparcV8ISelDAGToDAG.cpp | 27 +--
SparcV8Inst
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.63 -> 1.64
---
Log message:
remove some unused instructions
---
Diffs of the changes: (+6 -81)
SparcV8InstrInfo.td | 87 +++-
1 files changed, 6 insertions(+), 81
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.62 -> 1.63
---
Log message:
add andn/orn/xorn patterns. This allows us to compile this:
long %test(ubyte, short, long %X, long %Y) {
%A = xor long %X, -1
%B = and long %Y, %A
ret long %B
}
to this:
test:
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.5 -> 1.6
---
Log message:
Add support for 64-bit arguments
---
Diffs of the changes: (+12 -0)
SparcV8ISelDAGToDAG.cpp | 12
1 files changed, 12 insertions(+)
Index: llvm/lib/Target/SparcV8/Spa
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.4 -> 1.5
---
Log message:
Sparc doesn't have sext_inreg
---
Diffs of the changes: (+5 -0)
SparcV8ISelDAGToDAG.cpp |5 +
1 files changed, 5 insertions(+)
Index: llvm/lib/Target/SparcV8/SparcV8ISelDAGT
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.61 -> 1.62
---
Log message:
add patterns for FP stores
---
Diffs of the changes: (+12 -20)
SparcV8InstrInfo.td | 32
1 files changed, 12 insertions(+), 20 deletions(-)
Index: l
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.60 -> 1.61
---
Log message:
Add [reg+reg] integer stores
---
Diffs of the changes: (+15 -0)
SparcV8InstrInfo.td | 15 +++
1 files changed, 15 insertions(+)
Index: llvm/lib/Target/SparcV8/SparcV8Ins
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.27 -> 1.28
---
Log message:
add truncstore
---
Diffs of the changes: (+9 -3)
TargetSelectionDAG.td | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/TargetSelectionDAG.td
dif
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.59 -> 1.60
---
Log message:
Add store patterns
---
Diffs of the changes: (+6 -3)
SparcV8InstrInfo.td |9 ++---
1 files changed, 6 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/SparcV8/SparcV8Instr
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.58 -> 1.59
---
Log message:
add fp load patterns, switch rest of loads and stores to use addrmodes
---
Diffs of the changes: (+28 -30)
SparcV8InstrInfo.td | 58 +--
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.57 -> 1.58
---
Log message:
Add integer load[r+r] forms.
---
Diffs of the changes: (+23 -0)
SparcV8InstrInfo.td | 23 +++
1 files changed, 23 insertions(+)
Index: llvm/lib/Target/SparcV8/Sp
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelSimple.cpp updated: 1.92 -> 1.93
SparcV8RegisterInfo.cpp updated: 1.27 -> 1.28
---
Log message:
Rename load/store instructions to include an RI suffix
---
Diffs of the changes: (+51 -54)
SparcV8ISelSimple.cpp | 94 +++
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.56 -> 1.57
---
Log message:
Add patterns for the rest of the loads. Add 'ri' suffixes to the load and
store insts
---
Diffs of the changes: (+35 -31)
SparcV8InstrInfo.td | 66 +++---
Changes in directory llvm/lib/Target/SparcV8:
SparcV8AsmPrinter.cpp updated: 1.44 -> 1.45
SparcV8ISelDAGToDAG.cpp updated: 1.3 -> 1.4
SparcV8InstrInfo.td updated: 1.55 -> 1.56
---
Log message:
Add basic addressing mode support and one load.
---
Diffs of the changes: (+48 -3)
SparcV8AsmPrin
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.171 -> 1.172
---
Log message:
eliminate some redundancy
---
Diffs of the changes: (+8 -8)
X86InstrInfo.td | 16
1 files changed, 8 insertions(+), 8 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.54 -> 1.55
---
Log message:
Use a combination of sethi and or to build arbitrary immediates.
---
Diffs of the changes: (+7 -0)
SparcV8InstrInfo.td |7 +++
1 files changed, 7 insertions(+)
Index: llvm/lib
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrFormats.td updated: 1.11 -> 1.12
SparcV8InstrInfo.td updated: 1.53 -> 1.54
---
Log message:
Use sethi to build large immediates with zeros at the bottom
---
Diffs of the changes: (+14 -3)
SparcV8InstrFormats.td |3 ++-
SparcV8I
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.52 -> 1.53
---
Log message:
Add shift and small immediate support
---
Diffs of the changes: (+20 -6)
SparcV8InstrInfo.td | 26 --
1 files changed, 20 insertions(+), 6 deletions(-)
Index
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.51 -> 1.52
---
Log message:
Add some basic reg-reg instructions
---
Diffs of the changes: (+10 -5)
SparcV8InstrInfo.td | 15 ++-
1 files changed, 10 insertions(+), 5 deletions(-)
Index: llvm/lib/Ta
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrFormats.td updated: 1.10 -> 1.11
SparcV8InstrInfo.td updated: 1.50 -> 1.51
---
Log message:
Add empty patterns to all F3_1 instructions
---
Diffs of the changes: (+45 -43)
SparcV8InstrFormats.td |4 +-
SparcV8InstrInfo.td|
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.14 -> 1.15
---
Log message:
Darwin API issue: indirect load of external and weak symbols.
---
Diffs of the changes: (+8 -3)
X86ISelDAGToDAG.cpp | 11 ---
1 files changed, 8 insertions(+), 3 deletions(-)
In
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.49 -> 1.50
---
Log message:
Add some simple integer patterns. This allows us to compile this:
int %test(int %A) {
%B = add int %A, 1
%C = xor int %B, 123
ret int %C
}
into this:
test:
save -96, %sp, %
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.2 -> 1.3
---
Log message:
Implement ret with operand, giving us this:
int %test(int %A) {
ret int %A
}
---
Diffs of the changes: (+33 -2)
SparcV8ISelDAGToDAG.cpp | 35 +--
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrFormats.td updated: 1.9 -> 1.10
SparcV8InstrInfo.td updated: 1.47 -> 1.48
---
Log message:
Add empty patterns for F3_2 instructions
---
Diffs of the changes: (+58 -56)
SparcV8InstrFormats.td |6 +-
SparcV8InstrInfo.td| 108
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.48 -> 1.49
---
Log message:
Add a pattern for 'ret'. This now compiles:
void %test() { ret void }
:)
---
Diffs of the changes: (+1 -1)
SparcV8InstrInfo.td |2 +-
1 files changed, 1 insertion(+), 1 deletion
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.1 -> 1.2
---
Log message:
Implement LowerArguments, at least for the first 6 integer args
---
Diffs of the changes: (+63 -2)
SparcV8ISelDAGToDAG.cpp | 65 ++--
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