[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/SparcV8:

SparcV8ISelDAGToDAG.cpp updated: 1.8 -> 1.9
---
Log message:

implement div and rem


---
Diffs of the changes:  (+26 -0)

 SparcV8ISelDAGToDAG.cpp |   26 ++++++++++++++++++++++++++
 1 files changed, 26 insertions(+)


Index: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.8 
llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.9
--- llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.8 Sat Dec 17 16:30:00 2005
+++ llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp     Sat Dec 17 16:39:19 2005
@@ -65,6 +65,10 @@
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16  , Expand);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8   , Expand);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1   , Expand);
+
+  // Sparc has no REM operation.
+  setOperationAction(ISD::UREM, MVT::i32, Expand);
+  setOperationAction(ISD::SREM, MVT::i32, Expand);
   
   computeRegisterProperties();
 }
@@ -278,8 +282,30 @@
   
   switch (N->getOpcode()) {
   default: break;
+  case ISD::SDIV:
+  case ISD::UDIV: {
+    // FIXME: should use a custom expander to expose the SRA to the dag.
+    SDOperand DivLHS = Select(N->getOperand(0));
+    SDOperand DivRHS = Select(N->getOperand(1));
+    
+    // Set the Y register to the high-part.
+    SDOperand TopPart;
+    if (N->getOpcode() == ISD::SDIV) {
+      TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
+                                      CurDAG->getTargetConstant(31, MVT::i32));
+    } else {
+      TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
+    }
+    TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
+                                    CurDAG->getRegister(V8::G0, MVT::i32));
+
+    // FIXME: Handle div by immediate.
+    unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
+    return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
+  }    
   case ISD::MULHU:
   case ISD::MULHS: {
+    // FIXME: Handle mul by immediate.
     SDOperand MulLHS = Select(N->getOperand(0));
     SDOperand MulRHS = Select(N->getOperand(1));
     unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;



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