Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.58 -> 1.59 --- Log message: add fp load patterns, switch rest of loads and stores to use addrmodes --- Diffs of the changes: (+28 -30) SparcV8InstrInfo.td | 58 +++++++++++++++++++++++++--------------------------- 1 files changed, 28 insertions(+), 30 deletions(-) Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td diff -u llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.58 llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.59 --- llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.58 Sat Dec 17 14:26:45 2005 +++ llvm/lib/Target/SparcV8/SparcV8InstrInfo.td Sat Dec 17 14:32:47 2005 @@ -156,23 +156,21 @@ // Section B.2 - Load Floating-point Instructions, p. 92 def LDFrr : F3_1<3, 0b100000, - (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), - "ld [$b+$c], $dst", []>; + (ops FPRegs:$dst, MEMrr:$addr), + "ld [$addr], $dst", + [(set FPRegs:$dst, (load ADDRrr:$addr))]>; def LDFri : F3_2<3, 0b100000, - (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), - "ld [$b+$c], $dst", []>; + (ops FPRegs:$dst, MEMri:$addr), + "ld [$addr], $dst", + [(set FPRegs:$dst, (load ADDRri:$addr))]>; def LDDFrr : F3_1<3, 0b100011, - (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), - "ldd [$b+$c], $dst", []>; + (ops DFPRegs:$dst, MEMrr:$addr), + "ldd [$addr], $dst", + [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; def LDDFri : F3_2<3, 0b100011, - (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), - "ldd [$b+$c], $dst", []>; -def LDFSRrr: F3_1<3, 0b100001, - (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), - "ld [$b+$c], $dst", []>; -def LDFSRri: F3_2<3, 0b100001, - (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), - "ld [$b+$c], $dst", []>; + (ops DFPRegs:$dst, MEMri:$addr), + "ldd [$addr], $dst", + [(set DFPRegs:$dst, (load ADDRri:$addr))]>; // Section B.4 - Store Integer Instructions, p. 95 def STBri : F3_2<3, 0b000101, @@ -190,29 +188,29 @@ // Section B.5 - Store Floating-point Instructions, p. 97 def STFrr : F3_1<3, 0b100100, - (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), - "st $src, [$base+$offset]", []>; + (ops MEMrr:$addr, IntRegs:$src), + "st $src, [$addr]", []>; def STFri : F3_2<3, 0b100100, - (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), - "st $src, [$base+$offset]", []>; + (ops MEMri:$addr, IntRegs:$src), + "st $src, [$addr]", []>; def STDFrr : F3_1<3, 0b100111, - (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), - "std $src, [$base+$offset]", []>; + (ops MEMrr:$addr, IntRegs:$src), + "std $src, [$addr]", []>; def STDFri : F3_2<3, 0b100111, - (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), - "std $src, [$base+$offset]", []>; + (ops MEMri:$addr, IntRegs:$src), + "std $src, [$addr]", []>; def STFSRrr : F3_1<3, 0b100101, - (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), - "st $src, [$base+$offset]", []>; + (ops MEMrr:$addr, IntRegs:$src), + "st $src, [$addr]", []>; def STFSRri : F3_2<3, 0b100101, - (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), - "st $src, [$base+$offset]", []>; + (ops MEMri:$addr, IntRegs:$src), + "st $src, [$addr]", []>; def STDFQrr : F3_1<3, 0b100110, - (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), - "std $src, [$base+$offset]", []>; + (ops MEMrr:$addr, IntRegs:$src), + "std $src, [$addr]", []>; def STDFQri : F3_2<3, 0b100110, - (ops IntRegs:$base, IntRegs:$offset, i32imm:$src), - "std $src, [$base+$offset]", []>; + (ops MEMri:$addr, IntRegs:$src), + "std $src, [$addr]", []>; // Section B.9 - SETHI Instruction, p. 104 def SETHIi: F2_1<0b100, _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
