Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.1 -> 1.2
---
Log message:
Implement LowerArguments, at least for the first 6 integer args
---
Diffs of the changes: (+63 -2)
SparcV8ISelDAGToDAG.cpp | 65 ++++++++++++++++++++++++++++++++++++++++++++++--
1 files changed, 63 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.1
llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.2
--- llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.1 Sat Dec 17 01:47:01 2005
+++ llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp Sat Dec 17 02:03:24 2005
@@ -13,8 +13,11 @@
#include "SparcV8.h"
#include "SparcV8TargetMachine.h"
+#include "llvm/Function.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Support/Debug.h"
#include <iostream>
@@ -63,8 +66,66 @@
std::vector<SDOperand>
SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
- assert(0 && "Unimp");
- abort();
+ MachineFunction &MF = DAG.getMachineFunction();
+ SSARegMap *RegMap = MF.getSSARegMap();
+ std::vector<SDOperand> ArgValues;
+
+ static const unsigned GPR[] = {
+ V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
+ };
+ unsigned ArgNo = 0;
+ for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
{
+ MVT::ValueType ObjectVT = getValueType(I->getType());
+ assert(ArgNo < 6 && "Only args in regs for now");
+
+ switch (ObjectVT) {
+ default: assert(0 && "Unhandled argument type!");
+ // TODO: MVT::i64 & FP
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32: {
+ unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
+ MF.addLiveIn(GPR[ArgNo++], VReg);
+ SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
+ DAG.setRoot(Arg.getValue(1));
+ if (ObjectVT != MVT::i32) {
+ unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
+ : ISD::AssertZext;
+ Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
+ DAG.getValueType(ObjectVT));
+ Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
+ }
+ ArgValues.push_back(Arg);
+ }
+ }
+ }
+
+ assert(!F.isVarArg() && "Unimp");
+
+ // Finally, inform the code generator which regs we return values in.
+ switch (getValueType(F.getReturnType())) {
+ default: assert(0 && "Unknown type!");
+ case MVT::isVoid: break;
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
+ MF.addLiveOut(V8::I0);
+ break;
+ case MVT::i64:
+ MF.addLiveOut(V8::I0);
+ MF.addLiveOut(V8::I1);
+ break;
+ case MVT::f32:
+ MF.addLiveOut(V8::F0);
+ break;
+ case MVT::f64:
+ MF.addLiveOut(V8::D0);
+ break;
+ }
+
+ return ArgValues;
}
std::pair<SDOperand, SDOperand>
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