[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp SparcV8ISelDAGToDAG.cpp SparcV8InstrInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/SparcV8:

SparcV8AsmPrinter.cpp updated: 1.46 -> 1.47
SparcV8ISelDAGToDAG.cpp updated: 1.13 -> 1.14
SparcV8InstrInfo.td updated: 1.76 -> 1.77
---
Log message:

Add constant pool support, including folding into addresses.
Pretty print addresses a bit, to not print [%r1+%g0]: just print [%r1]


---
Diffs of the changes:  (+24 -2)

 SparcV8AsmPrinter.cpp   |   14 +++++++++++++-
 SparcV8ISelDAGToDAG.cpp |    8 ++++++++
 SparcV8InstrInfo.td     |    4 +++-
 3 files changed, 24 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp:1.46 
llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp:1.47
--- llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp:1.46  Sat Dec 17 20:27:00 2005
+++ llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp       Sat Dec 17 20:37:35 2005
@@ -185,8 +185,20 @@
 
 void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
   printOperand(MI, opNum);
+  MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType();
+  
+  if ((OpTy == MachineOperand::MO_VirtualRegister ||
+       OpTy == MachineOperand::MO_MachineRegister) &&
+      MI->getOperand(opNum+1).getReg() == V8::G0)
+    return;   // don't print "+%g0"
+  if ((OpTy == MachineOperand::MO_SignExtendedImmed ||
+       OpTy == MachineOperand::MO_UnextendedImmed) &&
+      MI->getOperand(opNum+1).getImmedValue() == 0)
+    return;   // don't print "+0"
+  
   O << "+";
-  if (MI->getOperand(opNum+1).getType() == MachineOperand::MO_GlobalAddress) {
+  if (OpTy == MachineOperand::MO_GlobalAddress ||
+      OpTy == MachineOperand::MO_ConstantPoolIndex) {
     O << "%lo(";
     printOperand(MI, opNum+1);
     O << ")";


Index: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.13 
llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.14
--- llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.13        Sat Dec 17 
20:27:00 2005
+++ llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp     Sat Dec 17 20:37:35 2005
@@ -75,6 +75,7 @@
 
   // Custom legalize GlobalAddress nodes into LO/HI parts.
   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
   
   // Sparc doesn't have sext_inreg, replace them with shl/sra
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16  , Expand);
@@ -251,6 +252,13 @@
     SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
     return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
   }
+  case ISD::ConstantPool: {
+    Constant *C = cast<ConstantPoolSDNode>(Op)->get();
+    SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32);
+    SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
+    SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
+    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
+  }
   }  
 }
 


Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
diff -u llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.76 
llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.77
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.76    Sat Dec 17 20:10:39 2005
+++ llvm/lib/Target/SparcV8/SparcV8InstrInfo.td Sat Dec 17 20:37:35 2005
@@ -660,6 +660,8 @@
 def : Pat<(i32 imm:$val),
           (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
 
-// Global addresses
+// Global addresses, constant pool entries
 def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
 def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
+def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
+def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;



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