Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.9 -> 1.10
---
Log message:
Implement 64-bit add/sub, make sure to receive and return 64-bit args with
the right halves in the right regs
---
Diffs of the changes: (+32 -4)
SparcV8ISelDAGToDAG.cpp | 36 ++++++++++++++++++++++++++++++++----
1 files changed, 32 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.9
llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.10
--- llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.9 Sat Dec 17 16:39:19 2005
+++ llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp Sat Dec 17 16:55:57 2005
@@ -109,10 +109,10 @@
break;
}
case MVT::i64: {
- unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
- MF.addLiveIn(GPR[ArgNo++], VRegLo);
unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
MF.addLiveIn(GPR[ArgNo++], VRegHi);
+ unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
+ MF.addLiveIn(GPR[ArgNo++], VRegLo);
SDOperand ArgLo = DAG.getCopyFromReg(DAG.getRoot(), VRegLo, MVT::i32);
SDOperand ArgHi = DAG.getCopyFromReg(ArgLo.getValue(1), VRegHi,
MVT::i32);
DAG.setRoot(ArgHi.getValue(1));
@@ -282,6 +282,34 @@
switch (N->getOpcode()) {
default: break;
+ case ISD::ADD_PARTS: {
+ SDOperand LHSL = Select(N->getOperand(0));
+ SDOperand LHSH = Select(N->getOperand(1));
+ SDOperand RHSL = Select(N->getOperand(2));
+ SDOperand RHSH = Select(N->getOperand(3));
+ // FIXME, handle immediate RHS.
+ SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag,
+ LHSL, RHSL);
+ SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH,
+ Low.getValue(1));
+ CodeGenMap[SDOperand(N, 0)] = Low;
+ CodeGenMap[SDOperand(N, 1)] = Hi;
+ return Op.ResNo ? Hi : Low;
+ }
+ case ISD::SUB_PARTS: {
+ SDOperand LHSL = Select(N->getOperand(0));
+ SDOperand LHSH = Select(N->getOperand(1));
+ SDOperand RHSL = Select(N->getOperand(2));
+ SDOperand RHSH = Select(N->getOperand(3));
+ // FIXME, handle immediate RHS.
+ SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
+ LHSL, RHSL);
+ SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH,
+ Low.getValue(1));
+ CodeGenMap[SDOperand(N, 0)] = Low;
+ CodeGenMap[SDOperand(N, 1)] = Hi;
+ return Op.ResNo ? Hi : Low;
+ }
case ISD::SDIV:
case ISD::UDIV: {
// FIXME: should use a custom expander to expose the SRA to the dag.
@@ -333,8 +361,8 @@
assert(N->getOperand(1).getValueType() == MVT::i32 &&
N->getOperand(2).getValueType() == MVT::i32 &&
N->getNumOperands() == 3 && "Unknown two-register ret value!");
- Chain = CurDAG->getCopyToReg(Chain, V8::I0, Select(N->getOperand(1)));
- Chain = CurDAG->getCopyToReg(Chain, V8::I1, Select(N->getOperand(2)));
+ Chain = CurDAG->getCopyToReg(Chain, V8::I1, Select(N->getOperand(1)));
+ Chain = CurDAG->getCopyToReg(Chain, V8::I0, Select(N->getOperand(2)));
return CurDAG->SelectNodeTo(N, V8::RETL, MVT::Other, Chain);
}
break; // Generated code handles the void case.
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