My next guess is that perhaps the kernel you're using doesn't
support process affinity? I'm not sure if that is possible, but it's a
guess.
As for why cpu1 stats are 0, either you haven't switched cpu
models yet or nothing has run on the second core (It's been idle). This
is likely given that
Just like the simulator said, the kernel version that the simulator
is reporting to the libc compiled in the app is too old for the libc/gcc
that you're using. Edit src/arch/x86/linux//syscalls.cc: and change the
linux version number to something newer.
Ali
On 09.08.2012 12:40,
Gihun wrote:
Hi Andrea,
The cachePorts parameter might do what you want on the d-side. There isn't
anything like that on the iside at the moment. You'd need to change the way the
fetch stage generates addresses to add the type of functionality.
Ali
On Aug 7, 2012, at 2:23 PM, Andrea Pellegrini wrote:
>
You need to compile the boot loader in system/arm/simple_bootloader and place
in in the binaries directory where you've placed the kernel. Also note that the
netperf benchmark isn't on the disk image you're using, so you'd need to fix
that.
Ali
On Aug 14, 2012, at 1:03 AM, Victor Ling wrote:
Both the virtual and physical address should be available in the Request object
that the Packet has a pointer to. Alternate approaches could include created a
specific packet type that contains the hint. Translation in SE mode is very
simple, as virtual memory is allocated by the program (throug
The disk image only has /bin/sh not bash on it. You likely have #!/bin/bash at
the top of your script so the interpreter isn't found.
Ali
On Aug 16, 2012, at 2:05 AM, Yi Liu wrote:
> Hi all
> The ARM Full-system staff(e.g. linux-arm-ael.img from gem5 download page)
> seems
> having problems w
committedInstructions are the number of machine instructions that have been
committed. The number of ops is greater than or equal than the number of
instructions. If an instruction is executed without being cracked its an op, if
it is cracked then everything it's cracked into are ops.
sim_ops a
I don't think you want to specify this in a cpu.cc file. For PARSEC
you want to modify the hooks library in parsec and add functions like
m5_checkpoint(0,0) and m5_dumpreset_stats(0,0) to the end of
__parsec_roi_begin() and probably and m5_exit(0) to __parsec_roi_end().
I imagine something simil
Some versions of systemtap do, however I'd still just instrument the
binaries/libraries with m5 ops: http://gem5.org/M5ops
Ali
On
17.08.2012 13:13, Anthony Gutierrez wrote:
> I've used an x86_64 host
with Ubuntu to build SystemTap modules and run them on Android ARM, so
it's doable. But, I
You can solve one of your probrems with the m5_work_begin()
m5_work_end() ops that record how long a "work item" takes to run,
however these are also marked non-speculative, although you could
probably allow them to be speculative if you wanted to and perhaps
cleanup the mess in the instruction
Could be something like the kernel version being too old for 4.3.2,
but that is just a guess.
Ali
On 17.08.2012 15:22, Anthony Gutierrez
wrote:
> Using the 4.3.2 versions (32/64 bit) of the Alpha
cross-compiler on gem5.org [1] results in statically compiled binaries
that seg fault; even a
Run with --frame-capture on the command line and you'll get a set of
frame every time it changes.
Ali
On 20.08.2012 16:56, Anthony
Gutierrez wrote:
> Because m5_exit caused the simulation it's highly
likely that bbench finished and exited correctly, due to the way the
benchmark is setup. L
You probably want a Stats::Value and set the functor() to a function
that returns the stat. That functor will be called when the stats are
dumped.
Ali
On 24.08.2012 19:29, Min Kyu Jeong wrote:
> Hi,
>
>
I am running a gem5 with some external simulator glued to it. I would
like to have a
I'm not sure exactly what you want? Do you want multiple workloads
with or without smt? In either case you're probably going to have to
modify configs/example/se.py a bit to suite your use case.
Ali
On
24.08.2012 21:07, Nyunyi Tshibangu wrote:
> I saw the following answer
in FAQ: "In SE mo
Hi Ali,
Yes, the hit latency is used for both. I'm going to post a
patch soon that provides a the ability to confider a different latency
for the response path.
Thanks,
Ali
On 24.08.2012 04:47, Ali chaker
wrote:
> Hi,
>
> I'm running bbench in gem5 with this configuration:
>
> Dcac
Hi Nathanaël,
The use of data instructions as branches is deprecated so we chose not to mark
them as branches and I'd hope you're not seeing too much use of them. If you
care the isBranch kwarg can be passed to the various data instructions in
src/arch/arm/isa/insts/data.isa like it is for the
sts/data.isa file and it
> seems to work.
>
> For the load instructions, LOAD_REG_AN_PN_SN_UN_WN_SZ4,
> LOAD_IMM_AN_PN_SN_UN_WN_SZ4, LOAD_REG_AY_PN_SN_UN_WN_SZ4 and
> LOAD_IMM_AY_PN_SN_UN_WN_SZ4 are not split in two and the control flag is not
> set when it is necessary.
Hrm. This
Hi Nathanaël,
I just posted some code that should address both the
issues you found. I haven't tested it yet, but let me know what you
find.
http://reviews.gem5.org/r/1376/
Thanks,
Ali
On 28.08.2012
12:01, Ali Saidi wrote:
> Hi Nathanaël,
>
> Sent from my ARM powered
d 3, and receives three
responses in cycle 10.
> Basically this is what is happening in the log
file.
> My conclusion would be that cache does not limit the number of
responses
> back to cpu and this mechanism (limiting responses) should
be provided in
> cpu.
>
> Thanks,
> Amin
>
&g
Did you have the disk image mounted when you ran gem5? I've seen
similar errors when someone has tried to modify a disk image while gem5
was running.
Ali
On 29.08.2012 16:17, Carole Wu wrote:
> I am
running bbench on ICS+ARM.
>
> Followed the instructions to download
the ics image & binar
If you want to run in SE mode one thread == one core. There is no scheduler and
if you want one, you'll need to write one yourself. If you're using FS mode
then the set affinity sys call is what you'll need to do.
Thanks,
Ali
On Sep 3, 2012, at 3:12 PM, Jun Pang wrote:
> Hi all,
>
> In the pr
Hi Abhinav,
It looks like your vnc client is doing something that we're not expected. We
don't have a fully featured vnc server in gem5. You could either add the
functionality we're missing or use the simple vncviewer client with the
-FullColor -PreferredEncoding=raw
Thanks,
Ali
On Sep 3, 20
You'll have to really dig into this code, and it depends on what you mean by
all PC accesses. THe PC is accessed to computer PC relative branches and it's
written when there is a branch commits. It can also get written when
instructions are squashed due to memory ordering issues, or similar conf
ve
> one instruction that has a problem (more event are detected, but only one is
> committed). It is a MicroLdrUop ("ldr_uop") instruction.
>
> Nathanaël
>
> Le 29/08/2012 20:39, Ali Saidi a écrit :
>> Hi Nathanaël,
>>
>> I just posted some code t
;
_changeset: 8642:549b72de8f72_
>> _tag: stable_2012_02_02_
>> _user: Ali
Saidi _
>> _date: Thu Dec 15 00:09:46 2011 -0500_
>> _summary: IO: Fix
bug in DMA Device where receiving a snoop on DMA port would cause a
panic._
> Today, I want to update to the ti
Hi Abhinav,
Please see inline.
On 06.09.2012 11:31, Abhinav
Kannan wrote:
> Hi,
>
> I removed the --frame-capture tag from the
gem5 command and changed the cpu-type to arm_detailed. I am still facing
the same issue in the checkSecurity() function. I wanted to know a few
additional details
were not flagged as control instructions (50%~60% on
> average, up to
98%) and for some other it was negligible (1% or even less).
>
>
Nathanaël
>
> Le 04/09/2012 03:10, Ali Saidi a écrit :
>
>> Hi
Nathanaël, How big was the stat before this out of curiosity? Have you
run
It depends on which architecture you're interested in, but the
answer is roughly yes. gem5 can run unmodified linux kernels. In some
cases some functionality (device drivers that we don't have device
models for) must be disabled. You can find config files on the download
page.
Ali
On 05.09.2
Hi Sameh,
If you could bisect the repository (see hg help bisect)
and figure out what changeset causes the issues (it should take ~10
tries) that would help in debugging the problem.
Thanks,
Ali
On
01.09.2012 19:12, Sameh Galal wrote:
> Hi everyone,
> I have used m5
couple of years ba
Hi Amit,
The stable version reports it's running Linux 2.6.29 when
an application asks and that is too old for the newest glibc you
compiled with. You can either get the development repository instead of
stable or change the 2.6.29 line in src/arch/arm/linux/process.cc to
3.0.0 or newer.
Tha
_UC))
>
(*uop)->setFlag(StaticInst::IsCondControl);
>
> Should be:
>
> if
(!(condCode == COND_AL || condCode == COND_UC))
>
(*uop)->setFlag(StaticInst::IsCondControl);
> else
>
(*uop)->setFlag(StaticInst::IsUncondControl);
>
> Thanks,
> Nathanaël
>
> Le
ondCode == COND_UC)) (*uop)->setFlag(StaticInst::IsCondControl); Should
be: if (!(condCode == COND_AL || condCode == COND_UC))
(*uop)->setFlag(StaticInst::IsCondControl); else
(*uop)->setFlag(StaticInst::IsUncondControl); Thanks, Nathanaël Le
06/09/2012 19:05, Ali Saidi a écrit :
>>
>
On Sep 11, 2012, at 3:28 PM, Nathanaël Prémillieu wrote:
> In this code, there are two MicroLdrUop that can be created. The second one
> is:
>
> *++uop = new MicroLdrUop(machInst, regIdx, INTREG_UREG0, up, addr);
>
> I believe this one is the ldr_uop that can be a branch.
>
> Thanks,
>
> Nat
It doesn't look like you have downloaded the kernel files or put
them in the right place.
Thanks,
Ali
On 14.09.2012 15:58, Munawira
Kotyad wrote:
> fatal: Could not load kernel file
/home/mkotyad/gem5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
_
Hi Nathanaël,
I'd guess it shouldn't be. I think it was that way
from when the ITSTATE bits were changed in the CPSR instruction. You
should be able to remove the "IsControl" flag and I think it will work.
Want to give it a try?
Thanks,
Ali
On 18.09.2012 09:14,
nathanael.premill...@irisa
t;
>
Nathanaël
>
> Le 18/09/2012 15:55, Ali Saidi a écrit :
>
>> Hi
Nathanaël, I'd guess it shouldn't be. I think it was that way from when
the ITSTATE bits were changed in the CPSR instruction. You should be
able to remove the "IsControl" flag and I think i
On 19.09.2012 14:30, Anthony Gutierrez wrote:
> I am trying to add
debug symbol information for the benchmark I am running. I can see where
the the debug symbol information is added from the kernel binary itself,
but is there a built-in way to pass a file with the symbol table
information for
The op class just controls the scheduling of the instruction, how
long it takes to execute and how pipelined the functional unit is. You
can create new functional units in the config files (by inheriting from
what is in src/cpu/FuncUnit.py) and the classes that ops can belong to
are in src/cpu/o
The setSingleStep code isn't particularly robust, but you should be
able to address the issues that you've described here. You can check if
the instruction is a 32bit thumb instruction by looking at the
ExtMachInst and adjust it appropriately. I don't know what version of
the simulator you're us
Hi Lluis,
I just tried it and it appears to be working. Could you
check again and see if you stil have the problem?
Thanks,
Ali
On
24.09.2012 10:31, Lluís Vilanova wrote:
> For some strange reason, the
javascript from recaptcha embedded at the bottom of
> the account
creation page for
Hi Mitch,
I wonder if this happens in the steady state? With the
implementation the store-set predictor should predict that the store is
going to conflict the load and order them. Perhaps that isn't getting
trained correctly with LLSC ops. You really don't want to mark the ops
as serializing a
Could you get a back trace when it happens. It's not a segmentation fault it's
a SIGABRT. You're running into a assertion and we need to know who is creating
this event that is causing you trouble.
Ali
On Sep 30, 2012, at 9:44 PM, Fangfei Liu wrote:
> I tried several different configuratio
run it on
other nodes, segmentation fault occurredafter it run for only several
seconds.
>>
>> -----
>>
>> FROM:
gem5-users-boun...@gem5.org [33] [gem5-users-boun...@gem5.org [34]] on
behalf of Ali Saidi [sa...@umich.edu [35]]
>> SENT:Sunday, September 30,
2012 11:32 PM
>
gc=9, argv=0x7fffe4f8) at build/ARM/sim/main.cc:57
>
> Do
you have any idea how to solve this problem? Thanks!
>
> Best regards
>
Fangfei
>
> -
>
> FROM:
gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on behalf of
Ali Saidi [sa...@umich.edu]
> SENT: Monday,
7;t get marked as a control
transfer instruction. I'm still missing an idea for a workaround to
this.
>
> Regards,
> Tobias
>
> Am 20.09.2012 18:09, schrieb Ali
Saidi:
>
>> The setSingleStep code isn't particularly robust, but you
should be able to address t
sizeof(MachInst));
> StaticInstPtr si =
tc->getDecoderPtr()->decode(inst, pc.pc());
> DPRINTF(Fail, "Instr:
%sn", si->disassemble(pc.pc()).c_str());
>
> Regards,
> Tobias
>
> Am
02.10.2012 16:34, schrieb Ali Saidi:
>
>> Hi Tobias,
>>
&g
em5/system/alpha/console/console.c so that I can use
more than 2 GB of main memory in my simulations?
>
> Thanks in
advance!
>
> Best regards,
> Alexandru Iordan
>
>
---------
> FROM: Ali Saidi ;
> TO: gem5 users mailing
list ;
> SUBJECT: Re: [gem5-
On 03.10.2012 10:12, Nilay Vaish wrote:
> On Wed, 3 Oct 2012,
Robert PINSKER wrote:
>
>> Ah. I figured it out. For the benefit of
anyone else reading this: If I use the directive DebugFlag('Tube') it
doesn't generate anything because my source file is tube.hh not Tube.hh.
So I have to use Deb
On 04.10.2012 11:43, Nilay Vaish wrote:
> There are specific
comments inline. Overall, I think you need to have a
> better
understanding of the options that you are trying to work with.
>
> On
Thu, 4 Oct 2012, Tao Zhang wrote:
>
>> Hi Nilay, Maybe I didn't make it
clear. What I want is to r
th debug flag ExecAll prints bxeq. So I tried
printing the machInst at
http://grok.gem5.org/source/xref/gem5/src/cpu/exetrace.cc#108 [2] and
it's showing 1012FFF13. I'm not sure why there is a difference and if
it's matters.
>>
>> Regards,
>> Tobias
>>
>>
Hi Robert,
It looks like you're trying to use gcc 3.4 to compile
the simulator. We don't support anything older than 4.3.
Ali
On
05.10.2012 06:50, Robert PINSKER wrote:
> I suddenly have this
problem. Since my last build, all I've done is try to sort out the
"type" and "system" variables
Hi Manu,
I don't know why you're seeing that issue,but you'd need
to provide a back trace to see which event is being scheduled that was
already scheduled. FYI, people normally boot with a simple CPU, take a
checkpoint, and then restore from that checkpoint. THis lest you get to
the region of
Hi Manu,
A gdb backtrace.
Thanks,
Ali
On 05.10.2012 10:34,
Manu Awasthi wrote:
> Ali Saidi umich.edu> writes:
>
>>
Hi Manu, I don't know why you're seeing that issue,but you'd need to
provide a back
>
> trace to see which event is being sched
t; line). So the load issues early, but the stores come in and clear the lock
> from the cacheline. So, either non-LLSC stores (from the same core)
> shouldn't clear the locks to a cacheline (src/cache/blk.hh:279). Or the
> store-set predictor should hold the linked-load until th
Hi Stjin,
Thanks for tracking this down. It sounds like it's a hisenbug.
On Oct 11, 2012, at 9:27 AM, Stijn Eyerman wrote:
> Hi,
>
> I encountered a nasty bug in gem5 regarding misspeculated load_locked
> instructions. I have some conceptual solutions, but I would like to ask your
> commen
Hi Manu,
PARSEC requires pthreads and there isn't a user-mode scheduling in gem5. The
easiest path forward is to run PARSEC on top of linux which will have all these
sys calls implemented. You could also try to compile parsec with the m5threads
code, but PARSEC's use of pthreads might require s
Yes it does. Normally people take a checkpoint after Linux boots and they start
their application of interest. When you restore from the checkpoint you'll only
get stats from the code that is executed after that. You can also use the m5
binary on the disk image (m5 resetstats m5 dumpresetstats
It's exactly the same see src/arch/arm/process.cc:69
You'll need to increase the version of linux reported.
Ali
On Oct 12, 2012, at 9:05 PM, manish jain wrote:
> Hi Everyone,
> After building the M5 for ARM ISA , I am trying to run an example in the
> simulator. But when I run this binary I a
From the error messages, clearly the compiler can't find a number of libraries.
You might try setting the LIBRARY_PATH (no LD) environment variable. You could
also try to compile the code within a ARM chroot on an ubuntu system.
Ali
On Oct 12, 2012, at 9:14 PM, Ding, Hongyuan wrote:
> Dear
It doesn't support these features "out-of-the-box." It would certainly be
possible to implement them, but you'll have to write code into the CPU models
to make it work.
Ali
On Oct 12, 2012, at 10:26 PM, mir shan wrote:
> Aslam O Alykum Ali and Hi community
>
> 1 Does this supported by Gem5
>
Hi Shervin,
They're nano-seconds.
Ali
On Oct 12, 2012, at 11:34 PM, shervin hajiamini wrote:
> Hi Andreas,
>
>
>
> Thank you very much for the clarification. Besides using
> periodicDumpStat(period), I found (through searching gem5 mailing list) that
> the stats can be also dumped periodi
It will take around 1.5 hours for android to boot completely and that number is
probably closer to 4 or 5 hours if you're running the debug binary which you
appear to being doing.
Ali
On Oct 13, 2012, at 3:40 AM, manish jain wrote:
> Hi,
> While running Android GingerBread simulation, my simul
I think we probably need to make the vnc code a bit more resilient to random
things trying to connect to the port.
It seems weird that there are so many port scanners trying to connect to the
vnc port on these machines.
You run add m5.disableAllListeners() to configs/example/fs.py near the bott
Hi Ben,
Unfortunately, we don't regularly test with 32 bit
systems. I think you probably need to add something like
-D_FILE_OFFSET_BITS=64 to the build because the disk image you're
accessing is likely larger.
Thanks,
Ali
On 15.10.2012 09:39,
Payne, Benjamin wrote:
> Hello,
>
> I am
Hi Amit,
It seems like you managed to find a case in the o3 cpu that isn't being
handled correctly. It looks like a load that is uncacheable isn't being
executed at the right time and that is what caused the panic. You'll need to
use the sequence number of the instruction and trace trough the
should be
> involved so I directly start working with that, I am very much poor
> programmer but trying with hardworking and hope for best
>
> regards
> Mir
>
>
>
>
> --- On Sat, 13/10/12, Ali Saidi wrote:
>
> From: Ali Saidi
> Subject: Re: [gem5-
Hi Dave,
It looks like the second system doesn't have a tlb
(this=0x0) in the #0 frame.
Thanks,
Ali
On 18.10.2012 11:14, David
Roberts wrote:
> Hello,
>
> I'm using the latest development
repository and ran into a problem when restoring checkpoints. I create
the checkpoint in atomic m
gem5 when its run with a frame buffer creates a vnc capable socket
so you can connect to it with at vnc client and control the keyboard and
mouse. It appears as though something is connecting to this socket and
saying the wrong things which confuses the rather simple vnc
implementation. You can
the Request class (there is already a context and thread
ID).
>>
>> I'm going to try this solution now, and report back if it
works.
>>
>> Regards,
>> Stijn
>>
>> On 10/12/2012 02:48 AM, Ali
Saidi wrote:
>>
>>> Hi Stjin,
>>>
>
How do you know the simulator is in the ROI?
Provided you know when it will be in the ROI, you can can periodically dump the
stats at that point.
Ali
On Oct 24, 2012, at 1:07 AM, shervin hajiamini wrote:
>
> Hello Fernando,
>
> Thanks for the link.
>
> It seems that for getting the periodi
Hi Shervin,
You can modify Simulation.py to run for however many ticks you need an then
return control to python:
m5.simulate(ticks_till_ROI)
statDump(10)
m5.simulate(m5.MaxTick)
Ali
On Oct 24, 2012, at 1:43 AM, shervin hajiamini wrote:
> Ali,
>
> Based on the stats I get for the ent
Hi Marko,
That seems like a good idea. Feel free to create a page
on the wiki and start to populate it.
Thanks,
Ali
On 25.10.2012
11:48, Marko Zivkovic wrote:
> Hello gem5 users,
>
> as I stated 3
days ago, I am new in gem5 world. I installed gem5 and my goal was to
run ffmpeg applic
Hi Erik,
I posted a patch last night that fixed some issues with
the local predictor, but it all certainly could be cleaned up. We'd be
very happy to commit patches that clean up and parameters and code to
address the issues you've identified.
Thanks,
Ali
On 25.10.2012
11:31, Erik Tomusk
Depending on where you look at it, it could be either.
Ali
On Oct 25, 2012, at 11:17 PM, Shen Yiran wrote:
> One more question will be is the nextPC associated with the DynInst the
> physically next instruction stored after the current one, or it is just
> predicted by some units??
>
> On Th
Hi Jordan,
Every dynamic instruction has a pointer to a static
instruction. All instructions in gem5 inherit from StaticInst and the
they are instantiated in the automatically generated decoder.cc files
(e.g. build/ARM/arch/arch/generated/decoder.cc). It's worth noting that
the output of the d
the second simulate should be end_tick_ROI - start_tick_ROI. You pass a
relative time to the function, not an absolute time.
Thanks,
Ali
On Oct 27, 2012, at 11:29 PM, shervin hajiamini wrote:
> Hi Ali, Andreas,
>
>
>
> I have tested dumping periodic stats for only ROI by putting the followi
Run scons link:
scons build/ALPHA_FS/m5.opt CC=/path/to/gcc-4.4.4
CXX=/path/to/g++-4.4.4
Ali
On Tue, 21 Jun 2011 01:55:58 -0400,
Thomas Patson wrote: Hi,
I'm a newbie to Gem5 and Scons. I was trying
to compile the ALPHA_FS system with Ruby but I got the 'operator
overload' error. Then upo
isTopLevel should be set on any cache that has a non-cache attached
above it.
Ali
On Thu, 23 Jun 2011 19:13:27 +0530, biswabandan panda
wrote:
Hi,
If i ll use !isTopLevel, does it mean l2 cache as well as
iocache or only l2 cache. plz do reply
--
_
You can take a look at the DEC Tsunami documentation and find an address that
is unassigned.
Ali
On Jun 27, 2011, at 5:00 PM, Alex Edwards wrote:
> Hi All,
>
> I am trying to add a simple simple BadDevice device to the ALPHA_FS system,
> but I am not sure what pio_addr to specify in FSConfig.
Run an ARM_FS binary with -n 2 or -n4 and you should have a multi-processor
system. You'll need to build a linux kernel starting with the configuration
file that is on the download page on the website. For multiple processors
you'll need to enable smp support. Additionally, you'll need to build
We run vortex nightly without any issues. vortex shouldn't be trying to use the
socket() syscall as far as I know. Additionally, I don't know what code would
print the, "GPT fault.." line as I can't find "GPT" in the source tree. Have
you made any changes to the simulator? What compiler are you
> Thanks again,
> Alex Edwards
>
>
>
> On Mon, Jun 27, 2011 at 7:20 PM, Ali Saidi wrote:
> You can take a look at the DEC Tsunami documentation and find an address that
> is unassigned.
>
> Ali
>
> On Jun 27, 2011, at 5:00 PM, Alex Edwards wrote:
>
>
amily 1
> [0.000120] msgmni has been set to 244
> [0.000121] io scheduler noop registered (default)
> [0.000121] CLCD: RealView hardware, XVGA display
>
>
> Does anyone have any ideas?
>
> Thanks in advance.
>
> ajonwa
>
> PS: I am also attaching
This is the simulator saying that you don't have enough memory available. Are
you running on a 32 bit host? Are you trying to simulate more than 1GB of
memory?
Ali
On Jul 1, 2011, at 12:17 AM, Srinivasulu Naik B. wrote:
> When I run the below command I got the error. So please suggest me what
The source to build it is in system/alpha/palcode.
Ali
On Jul 1, 2011, at 11:49 AM, 王澍 wrote:
> Hi Alex,
>
> Thank you for your help. It works now.
>
> I have another question. I found If I want to run ALPHA_FS with 8 cores or
> more, I need to replace normal ts_ospal by tsb_ospal.
> Could yo
The code is located in system/alpha/palcode and there is a makefile in there.
You'll need Alpha cross compliers.
Ali
On Jul 3, 2011, at 3:00 PM, 王澍 wrote:
> Hi,
>
> Does anyone know how to compile a new PAL code. I use ALPHA_FS system. If I
> will use BigTsunami, I need to modify the PAL code
>
> Am I missing something obvious?
>
> Thanks
> ajonwa
>
>
>
>
>
>> - Original Message -
>> From: Ali Saidi
>> Sent: 06/29/11 01:02 AM
>> To: gem5 users mailing list
>> Subject: Re: [gem5-users] ARM MP FS
>>
>> disable local_t
Hi Brad,
I think this depends on if the platform expects a TCB or
a DTV at the thread pointer. Different platforms sparc, alpha, x86, ARM
expect different things and an ifdef controls which one should be there
in the code somewhere.
Thanks,
Ali
On Wed, 6 Jul 2011 16:36:32
-0500, "Beckman
On Jul 6, 2011, at 9:53 PM, Meng Dong wrote:
> Hi all
> My subject is about CMP/SMT hybrid architecture but it seems I haven't made
> some progress
>
> I found that The SPARC architecture in gem5 is a SPARC core and it support SMT
> So I want to use two SPARC cores to achieve a basic CMP/SMT
In almost all cases the bits that control thing like enabling/disabling
caches/prefechers/branch predictors/etc are ignored by gem5. The presence of
these types of structures is dependent on the gem5 configuration and not the
architecture control registers. By default there is no prefetcher enab
- Original Message
> From: Ali Saidi
> To: gem5 users mailing list
> Sent: Wed, 6 July, 2011 9:27:27 AM
> Subject: Re: [gem5-users] MMAP Error
>
> This is the simulator saying that you don't have enough memory available. Are
> you running on a 32 bit host? Are
Are you using the latest gem5 code? How long does it take for you to
reach this issue?
The issue is that these instructions have been created, but they haven't
been deleted. This means that some resource in the pipeline is holding a
reference to the instruction and it's not being deleted, the
Hi George,
there isn't a way built into the example configuration scripts to
connect more than one disk image, but if you look for how the
--disk-image (disk_image in the python files) is used you can see that
the parameter is ultimately passed from fs.py into FSConfig.py which
adds that disk
You can take that one m5_struct.patch and apply it alone to the kernel
you're trying to use.
Ali
On 07.11.2014 03:46, Sanem Arslan via gem5-users wrote:
> Hi Anthony,
> To apply these patches, should I follow the steps in the following
> link? http://www.m5sim.org/Compiling_a_Linux_Kernel
If you haven't specified --caches there aren't any caches in the system.
A configuration file the kernel is reading specifies caches exist for
the kernels purposes, but there aren't any in the system.
Ali
On 20.11.2014 15:43, Thom Popovici via gem5-users wrote:
> Hi!
>
> I would like to
The hdlcd should be controlled by the kernel, not by a application as it won’t
have a mapping for the physical addresses. If you download the latest kernels
from the website they support the hdlcd.
Ali
On Nov 27, 2014, at 3:05 AM, via gem5-users wrote:
> Hi,everyone:
>
> I would like to make
You can dump the stats every 1000 instructions, but it will be quite slow. You
can modify configs/common/Simulate.py to call m5.stats.dump() and
m5.stats.reset() on every exit from the simulation loop which you can program
with cpu.max_insts_any_thread.
Ali
> On Dec 31, 2014, at 3:37 AM, Kuma
Try now?
Thanks,
Ali
On 2/11/15, 11:36 AM, "Dave Werner via gem5-users"
wrote:
>Rizwana Begum via gem5-users gem5.org> writes:
>
>>
>> Hello All,
>> I am trying to register on review board, but end up with error "An
>internal error occurred: 50EA8B0A168C0.A8CAE85.ED001888".I have been
>tryin
I don’t see any errors and I’m able to create a new user.
Have you tried a different user name? Different web browser?
Thanks,
Ali
From: Rizwana Begum mailto:rizwana@gmail.com>>
Date: Wednesday, February 11, 2015 at 4:59 PM
To: Ali Saidi mailto:ali.sa...@arm.com>>, gem5 users m
m5sim.org site.
Thanks,
Ali
From: Guru Prasad mailto:gurup...@buffalo.edu>>
Date: Thursday, February 12, 2015 at 8:51 AM
To: Rizwana Begum mailto:rizwana@gmail.com>>, gem5
users mailing list mailto:gem5-users@gem5.org>>
Cc: Ali Saidi mailto:ali.sa...@arm.com>>
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