Hi Nathanaël,
I'd guess it shouldn't be. I think it was that way from when the ITSTATE bits were changed in the CPSR instruction. You should be able to remove the "IsControl" flag and I think it will work. Want to give it a try? Thanks, Ali On 18.09.2012 09:14, nathanael.premill...@irisa.fr wrote: > Hi All, > > It seems that instructions that writes into some control registers (CPSR > and CPACR) are set as control instructions (flag IsControl is set). This > is due to the definition and the use of cntrlReg in > src/arch/arm/isa/operands.isa: > > (l.120) > def cntrlReg(idx, id = srtNormal, type = 'uw'): > return ('ControlReg', type, idx, (None, None, 'IsControl'), id) > > (l.238) > 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr), > 'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr), > > (l.246) > 'Cpacr': cntrlReg('MISCREG_CPACR'), > > I was thinking that IsControl flag is only set for branch instruction > i.e. instructions that modify the PC. Am I wrong? > > Thanks, > > Nathanaël > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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