You'd probably need to start with src/cpu/o3/* if you're interested in the o3 cpu or src/cpu/inorder if you're interested in an in-order cpu.
Ali On Oct 15, 2012, at 6:58 AM, mir shan wrote: > Thanks Ali > sorry to bother you again but can identify specially which files should be > involved so I directly start working with that, I am very much poor > programmer but trying with hardworking and hope for best > > regards > Mir > > > > > --- On Sat, 13/10/12, Ali Saidi <sa...@umich.edu> wrote: > > From: Ali Saidi <sa...@umich.edu> > Subject: Re: [gem5-users] SOE(Switch on Event) multithreading > To: "gem5 users mailing list" <gem5-users@gem5.org> > Date: Saturday, 13 October, 2012, 7:26 PM > > It doesn't support these features "out-of-the-box." It would certainly be > possible to implement them, but you'll have to write code into the CPU models > to make it work. > > Ali > > On Oct 12, 2012, at 10:26 PM, mir shan wrote: > >> Aslam O Alykum Ali and Hi community >> >> 1 Does this supported by Gem5 >> modified the simulator to support SOE(Switch on Event) multithreading, >> switching on L2 cache misses (last-level cache misses). >> >> 2. Which files involved in this work. >> >> regards >> Mir >> >> >> >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > -----Inline Attachment Follows----- > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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