Hi Andrea, The cachePorts parameter might do what you want on the d-side. There isn't anything like that on the iside at the moment. You'd need to change the way the fetch stage generates addresses to add the type of functionality.
Ali On Aug 7, 2012, at 2:23 PM, Andrea Pellegrini wrote: > Hi all, > I am wondering if there is any quick way to increase the number of ports of a > O3 CPU to the ICache and DCache (or mimic a similar behavior). > > Did anyone look at it yet? > Thanks, > -Andrea > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
