Re: [gem5-users] gem5ToMcPAT v0.1

Hi Andreas, Thanks for the link. Sounds really interesting. Are the power models extensible to architectures other than Big.little? It seems like the tool targets mobile architectures at this point. Thanks, Amin On Thu, Apr 21, 2016 at 3:09 AM, Andreas Hansson wrote: > Hi all, > > McPAT defini

Re: [gem5-users] Reading Cache hits and misses dynamically

Kumail, If you want getting MPKI for the whole execution (i.e., beginning from the time you reset stats until you dump stats), you can simply use the number of misses and committed instructions to calculate. But if you want MPKI for each 1000-instruction phase, then you need to modify the code (an

Re: [gem5-users] Integrated DRAMPower model

To correctly get energy numbers you need to set the right set of current values (e.g. IDD2N) for your specific device. For example, 1Gb DDR3 devices have different current values from 8Gb DDR3 devices. You can find those values in manufacturers dustsheets. Each rank has a number of devices (device

Re: [gem5-users] DRAM memory access latency

Prathap, You are probably missing DRAM queuing latency (major reason) and other on-chip latencies (such as bus latency) if any. Thanks, Amin On Tue, Nov 4, 2014 at 1:28 PM, Prathap Kolakkampadath via gem5-users < gem5-users@gem5.org> wrote: > Hello Users, > > I am measuring DRAM worst case memo

Re: [gem5-users] Unit of avg_miss_latency

pico second. Each tick is a pico second in gem5. Amin On Tue, Oct 14, 2014 at 7:53 PM, Prathap Kolakkampadath via gem5-users < gem5-users@gem5.org> wrote: > Hi Users, > > Below is the avg miss latency for l2 captured from stats.txt. What is the > unit of this? Does this mean 230ns? > > > system.

Re: [gem5-users] Tracking DRAM read/write requests

This is very dependent on your bandwidth test program. May be your miss rate is low... may be your programs cannot benefit from memory level parallelism... Use gem5 stats to dig in further. There are some programs out there that can stress dram utilization. But writing a good one is not that hard.

Re: [gem5-users] Query regarding DRAM controller's FR-FCFC scheduler implementation.

Prathap, As far as I remember, it choses the first request (oldest one) among hits. It starts from head of the queue and once there is a hit, you have got "the first come among multiple row hits." Thanks, Amin On Wed, Oct 1, 2014 at 1:59 PM, Prathap Kolakkampadath via gem5-users < gem5-users@gem

[gem5-users] Performance change after changeset 10338

Hi, After updating to changeset 10338 (condition code registers for ARM), I observed some (relatively significant) performance improvement. On a particular workload which I usually check when I update gem5, the execution time improves by 9%. It seems like the perf improvement is caused by having m

Re: [gem5-users] O3 fetch throughput when i-cache hit latency is more than 1 cycle

. > > I haven't yet seen a case where this adding additional latency later to > make up for the lack of real instruction cache latency makes much of a > difference. > > > > On Tue, Aug 26, 2014 at 11:32 AM, Amin Farmahini via gem5-users < > gem5-users@gem5.org>

[gem5-users] O3 fetch throughput when i-cache hit latency is more than 1 cycle

Hi, Looking at the codes for the fetch unit in O3, I realized that the fetch unit does not take advantage of non-blocking i-caches. The fetch unit does not initiate a new i-cache request while it is waiting for the an i-cache response. Since fetch unit in O3 does not pipeline i-cache requests, fet

Re: [gem5-users] CPU ID in cache and dram controller

Use srcMasterId to identify the original requester. Thanks, Amin On Sat, Jul 26, 2014 at 1:23 AM, Debiprasanna Sahoo via gem5-users < gem5-users@gem5.org> wrote: > Hi, > > I need to manipulate requests received at cache and dram_ctrl on the basis > of their original CPU/Thread source. I tried t

Re: [gem5-users] No writeback latency in classical cache？

Well, grep does not result in any readLatency ... hitLatency and responseLatency are what you are looking for and they are used for both reads and writes. See src/mem/cache/base.cc. Thanks, Amin On Thu, Jul 10, 2014 at 8:31 PM, Qi Jia via gem5-users wrote: > Hi, everyone, > > I am looking at c

[gem5-users] Power down state in memory controller

Hi, It seems like in the current version of gem5, the power down state in the memory controller is not used. No transition is made to this state (to either ACT_PDN or PRE_PDN). Am I missing something? I would guess some changes are needed to support this power state as the current memory controlle

Re: [gem5-users] McPAT Parser

In O3, numCycles includes idleCycles. So busy cycles is numCycles - idleCycles. As a side note, there is also quiesceCycles. Thanks, Amin On Tue, Apr 15, 2014 at 2:45 PM, Tiago Mück wrote: > Hi Lluíz, > > I've noticed that you are using this mapping in your core template: > > > >

Re: [gem5-users] Casting type of numCycles to other fundamental data types

You can use numCycles.value(). See statistics.hh file. Thanks, Amin On Tue, Mar 11, 2014 at 6:37 PM, shervin hajiamini wrote: > Hi all, > > In gem5 (base.hh file) 'numCycles' is declared as 'stats::Scalar'. I want > to cast 'numCycles' to other C++ variable types like 'integer' or 'double', > h

Re: [gem5-users] Running a simple C program as a benchmark in Full System Mode

Read http://www.m5sim.org/Running_gem5 from "Booting Linux." After booting linux, you can use either terminal or .rcS to run the executable of your program (which should be present in your disk image). Thanks, Amin On Tue, Mar 11, 2014 at 1:43 PM, tanmayGadre wrote: > I want to run my C progra

Re: [gem5-users] gem5 ARM L2 Cache, exclusive or inclusive or neither?

As far as I know, gem5 classic cache is non-inclusive. I cannot speak for ARM caches. Thanks, Amin On Sat, Mar 1, 2014 at 8:46 PM, Peng Wei wrote: > Hi there, > > I was wondering if anybody could help me clarify which kind of cache > mechanism adopted for gem5's ARM L2 Cache. Is it strictly in

Re: [gem5-users] Fwd: McPAT

These patches are not submitted yet and as far as I know such a feature does not exist yet. Why don't you use McPAT from HP until these patches get pushed in? Amin On Thu, Feb 6, 2014 at 1:41 PM, Sudarshan wrote: > Can anyone respond to the above comments and tell us what the use of the > mcpa

Re: [gem5-users] Per core DFS implementation

Hi Srini, You could have a separate clock domain for each core and each clock domain has its own clock period. Take a look at src/sim/clocked_object.hh . And I am no expert, so hopefully experienced users could provide more detailed info. Thanks, Amin On Wed, Feb 5, 2014 at 12:23 AM, Srinivasan

Re: [gem5-users] implement cache flush in classic memory model

Hi Fangfei, If you want to implement it using *functional *accesses (*zero *latency), you need to 1. Writeback every dirty lines in the cache. 2. Invalidate all lines in the cache. For invalidation and writeback you can use visitor functions. Here is a piece of code that might help you. template

Re: [gem5-users] The frequency of memory requests being issued each cycle

wonder how many cycles in which a new > load or store request is issued. This number cannot be got via dividing # > the number of loads and stores by # the number of cycles, since maybe > more than one load or store be issued in the same cycle. > > Could you give some advice? &g

Re: [gem5-users] The frequency of memory requests being issued each cycle

If you are using O3, you can add some counters in LSQ to count the number of loads and stores issued. That is fairly simple. You may also take a look at stats file. You may be able to extract that information from stats even w/o modifying the code. Thanks, Amin On Mon, Dec 9, 2013 at 11:41 AM, Y

Re: [gem5-users] Weird Results: Overall L2 miss latency > Number of ticks simulated

MSHR, non blocking cache, memory level parallelism. On Dec 8, 2013 1:13 AM, "Hossein Nikoonia" wrote: > Dear List, > > I am running an experiment with gem5 in X86 + SE + Classic Memory. > The system has two cpus and runs two workloads. The workload is very > simple. It accesses memory in each cyc

Re: [gem5-users] Patch for a particular revision of gem5

You need to specify a changeset number, like 9987. Amin On Thu, Dec 5, 2013 at 8:07 AM, senni sophiane wrote: > I tried "hg diff -r 5e8970397ab7" but I have the error : unknown > revision '5e8970397ab7' ! > > Cordialement / Best Regards > > SENNI Sophiane > Ph.D. candidate - Microelectronics >

Re: [gem5-users] regarding mcpat

use it uses the snooping protocol. I would disable the cache > > directories. Correct me if I'm wrong please. > > > > Regards, > > > > -- > > Fernando A. Endo, PhD student and researcher > > > > Université de Grenoble, UJF > > France > > > >

Re: [gem5-users] regarding mcpat

This might give you some idea. https://www.cl.cam.ac.uk/~acr31/sicsa/mcpat-template.xml Amin On Wed, Nov 20, 2013 at 8:58 AM, Mahmood Naderan wrote: > Hi, > While porting stats from gem5 to mcpat, I could not find the > counterpart of the following stats. > > 1- Shall we use the same L1D stats

Re: [gem5-users] GEM5 to McPAT

This is a McPAT-related question, not a gem5 one. In McPAT, throughout and latency in xml file are in fact cycle time and access time in cacti. So, McPAT tries to optimize the cache for the specified throughput (cycle time) and latency (access time). Amin On Mon, Oct 28, 2013 at 7:11 PM, Ivan St

[gem5-users] Operation latency of SIMD instructions in O3 ARM

Hi All, The operation latency of some SIMD instructions given in configs/common/O3_ARM_v7a.py does not seem right to me. For example, the operation latency of SimdFloatMultAcc is only 1 cycle and operation latency of SimdFloatDiv is only 3 cycles. These latency values seem too low. Any thoughts?

Re: [gem5-users] (no subject)

Tony, I noticed the same thing as well and as you mentioned the perf penalty could be really high. http://www.mail-archive.com/gem5-users@gem5.org/msg05894.html I don't know what the reason could be, but I was able to fix this. If I remember right, to prevent squashing, you need to mark those load

Re: [gem5-users] Use of Communication Monitor for cache latency

There is not much info in this regard and I am no expert because I don't use this regularly. Here is some info I found when I used Monitor. You first need to connect the Monitor. You can do something like this: system.monitor = CommMonitor(trace_file="comm.trace") system.membus.master = sy

Re: [gem5-users] Cache coherence message trace

You need to determine which cache model you want to use. Implementation of ruby is very different from that of classic and results in different stats for multiprocessor systems. To answer your question, use --debug-help to see a list of all trace flags available. I'd suggest you add the CoherentBus

[gem5-users] SIMD-like load operations in ARM

I am trying to implement wide SIMD-like load/store operations, and I found that some TLB flags are set based on memory request size. Those ArmFlags are defined in arch/arm/tlb.hh and it seems like the maximum supported size is 64 bytes (AlignOctWord). 1. I'd like to add flags for other sizes, but

Re: [gem5-users] Is it right sanity check in simple_dram.cc??

Thanks Andreas! :) Amin On Mon, Jul 29, 2013 at 12:56 AM, Andreas Hansson wrote: > Hi all, > > We have got a fix, but for now I will commit a change that turns it into > a warning instead of a fatal. I don't want Amin to have to rebase his patch > (again) :-) > >

Re: [gem5-users] Is it right sanity check in simple_dram.cc??

I have got that panic error a few times so far when the running application is memory-intensive with low temporal locality. I could not figure out why this panics, but I don't think they consider only first and last activations. A list of past X activations is kept, where X is the maximum number of

[gem5-users] Cache flushing in classic cache model

Hi, I'd like to implement a cache flushing mechanism to writeback dirty lines to memory in classic cache model. I am using timing memory model, but currently don't care about getting the correct timing. As a first step, I would like to get the correct functionality without worrying about timing (i

Re: [gem5-users] (no subject)

s to set the value, what additional steps or >> procedure do i need to perform? Do I need to do anything with SWIG or >> something? >> >> Thanks, >> Zheng Wu >> >> >> On 2013-07-16, at 8:23 PM, Amin Farmahini wrote: >> >> The last thing th

Re: [gem5-users] (no subject)

The last thing that Tao forgot to mention is to use options.robsize to set the value of numROBEntries (numROBEntries is defined in src/cpu/o3/O3CPU.py). Amin On Tue, Jul 16, 2013 at 5:06 PM, Tao Zhang wrote: > Hi Mahshid, > > ** ** > > You can use the “add_option” to add any desired option

Re: [gem5-users] Prefetcher implementation

If you are talking about cache prefetchers, there are a few prefetchers implemented in gem5. You can start by reading their codes. Be careful about using them as they are not great. I would not be surprised, If you see any weird behavior. What's your specific question? Amin On Fri, Jul 12, 2013

Re: [gem5-users] Instruction Execution Time

I think this is what you are looking for: http://www.m5sim.org/Visualization Amin On Tue, Jul 2, 2013 at 8:29 PM, Jianghao wrote: > Is there any way I can trace instruction execution time at different > pipeline stages? > For example, an ARM instruction goes through fetch, decoding and may be

[gem5-users] Identify the issuer of a request

Hi All, If a request comes from a processor, the contextId() function can be used to identify the processor. But when a request is a writeback, how can I find out what cache or device the request originates from? Thanks, Amin ___ gem5-users mailing list

Re: [gem5-users] masterID for snooping

Do we have any control on how a masterID is assigned? I mean, how can I make sure a specific core always gets a pre-defined master ID? Thanks, Amin On Mon, Jun 24, 2013 at 4:58 AM, Andreas Hansson wrote: > Hi Uday, > > Sure. In that case I'd say add another unique value and (re)use that for >

Re: [gem5-users] Some notes about SimpleDRAM controller

Andreas, I just submitted a patch regarding this email. Please go over it. http://reviews.gem5.org/r/1927/ Thanks, Amin On Mon, Jun 10, 2013 at 11:46 PM, Amin Farmahini wrote: > Thanks for the response Andreas. I am willing to work on a patch and > submit it, if it can be done fairly

Re: [gem5-users] Default Cache Memory Bank Configuration?

Classic model does not support multi-bank caches. I don't know about Ruby. Amin On Thu, Jun 13, 2013 at 8:00 PM, Gabriel Yessin wrote: > Specifically for ARM L1/L2 caches using the default memory, e.g.: > > ./build/ARM/gem5.fast ... configs/example/fs.py ... --caches > --cpu-type=detailed --l1

Re: [gem5-users] Some notes about SimpleDRAM controller

the cache > line size we avoid "illegal" configurations. I hope that both brings some > answers as to why it looks the way it does. > > If you want to take a stab at addressing the issues go ahead and submit > a patch to the review board. > > Thanks, > > Andre

Re: [gem5-users] ARM InOrder implement

Yes, as far as I know it does not work. O3 to InOrder hack is the way to go. Thanks, Amin On Fri, Jun 7, 2013 at 4:56 PM, Xiangyang Guo wrote: > Hi, gem5-users, > > I want to use the InOrder CPU for ARM ISA, but it is not implemented. in > the post, > http://thread.gmane.org/gmane.comp.emulato

[gem5-users] Some notes about SimpleDRAM controller

Hi All, 1. In the SimpleDRAM controller, it is assumed that the DRAM burst size equals to the cache line size. I think it makes more sense to use a separate variable for burst size and get rid of bytesPerCacheLine. The reason is that the DRAM controller could be connected (through a bus) to caches

[gem5-users] Multi-port DRAM controllers

Hi, My question is how to model a multi-port DRAM controller using SimpleDRAM? Let's say a DRAM controller is connected to two buses. In this case, the DRAM controller should have two ports, each connected to a bus. Thanks, Amin ___ gem5-users mailing l

Re: [gem5-users] Simple cache model and cachePorts limit

inate in the core (e.g. data from L2 to L1D). > > So it looks like cachePorts gives 80% of the desired behavior with 20% of > the effort. Given that there's nothing better on the horizon, I can try to > get cachePorts to work again and make a patch. > > Any thoughts? >

Re: [gem5-users] Simple cache model and cachePorts limit

See below. Amin On Fri, May 10, 2013 at 10:10 AM, Erik Tomusk wrote: > Hi All, > > I've been looking at L1 dcache ports (ports as in the number of read/write > requests that a physical cache can service at one time, not ports as the > abstraction gem5 uses to connect memory devices). At the mom

[gem5-users] SimpleDRAM accuracy

Hi, Comparing SimpleDRAM model and DRAMSim2 model, I was wondering how timing accurate SimpleDRAM is for memory-intensive applications? This might be a question for Andreas and Tao and I know this is a very general question, but any thoughts on this would be appreciated. Andreas mentioned that Sim

Re: [gem5-users] Question about SimpleMemory latency

A latency of 3 means 3 ps, or 30 ns. To change it, you may edit src/mem/SimpleMemory.py or may define a new command option using the configs/common/Options.py file. Thanks, Amin On Tue, May 7, 2013 at 12:21 PM, David Gloe wrote: > Hello, > > For a default memory configuration using S

Re: [gem5-users] SE mode : run a program with an argument

Use --options="your arguments" . Thanks, Amin On Fri, May 3, 2013 at 12:02 PM, Maxime Chéramy wrote: > Hello, > > I have a bunch of benchmarks that take arguments. However, when I try to > run them, I have this error: > > Error: script doesn't take any positional arguments >> > > Which makes pe

[gem5-users] Classic memory stats: overall_accesses

I have a question about the stats generated in classic memory model. I realized that overall_access is always the sum of ReadReq_accesses and ReadExReq_accesses. system.l2.ReadReq_accesses::total 3816827 system.l2.Writeback_accesses::total 5433149 system.l2.UpgradeReq_accesse

Re: [gem5-users] what is the response_latency in "BaseCache.py"?

This explains what response latency is. Thanks, Amin On Sun, Mar 17, 2013 at 9:44 PM, Pavlos Maniotis wrote: > Hello everyone, > > Could you please explain me what exactly is the response_latency in > BaseCache.py and its relationship to the hit latency? > > T

Re: [gem5-users] O3CPU

, Mar 7, 2013 at 7:31 PM, ali bagherian wrote: >> >>> Hi Amin, >>> >>> Thank you for your help. >>> Do I need to recompile the Gem5 after changing fetchWidth? I found this >>> parameter in O3CPU.py file. >>> >>> Thanks, >>&

Re: [gem5-users] O3CPU

Change fetchWidth parameter. Thanks, Amin On Thu, Mar 7, 2013 at 11:51 AM, ali bagherian wrote: > Hi, > > Can we change the number of instruction we can fetch at the same time? I > want to run the simulation with O3CPU model but I do not want to fetch > several instruction at the same time. > >

Re: [gem5-users] Default Memory Hierarchy Port Configuration?

Gabriel, There is a bus between L1 and L2. So the connection is between L1 and L2 is not direct. As Tao metined take a look at configs/common/CacheConfig.py for more info. To make sure you get what you want, go over the generated config.ini file. It explains your system architecture in detail. Ea

Re: [gem5-users] Question about PacketQueue::scheduleSend

Mitch, regarding our conversation last night and your post, you may want to take a look at http://www.mail-archive.com/gem5-users@gem5.org/msg04107.html Thanks, Amin On Fri, Feb 15, 2013 at 12:05 PM, Mitch Hayenga < mitch.hayenga+g...@gmail.com> wrote: > Nevermind, o3 has this problem as well..

Re: [gem5-users] config.ini doubt

> [system.cpu2] > --deleted-- > clock=640 > --deleted-- > > [system.cpu3] > --deleted-- > clock=500 > --deleted-- > > > > On 13/02/13 21:00, Amin Farmahini wrote: > > It is clock frequency in MHz. > > Thanks, > Amin > > > On Wed, Feb 13, 201

Re: [gem5-users] config.ini doubt

It is clock frequency in MHz. Thanks, Amin On Wed, Feb 13, 2013 at 2:33 PM, Jyothish wrote: > Hello folks, > I am starting this as an independent query. In config.ini, the clock set > out is not the same as the clock in the cpu models. It is seems to be the > number of clock ticks instead of t

Re: [gem5-users] changing individual frequencies pointers requested

I guess it would be sufficient. I don't use fs.py so I might be wrong. What you can do is to run it and check the config.ini file. This file clearly specifies the frequency of each processor. Thanks, Amin On Tue, Feb 12, 2013 at 10:57 AM, Jyothish wrote: > Hi, > I am new to GEM5 and am trying

Re: [gem5-users] Timing CPU scheduling behaviour for different frequencies

When you change the frequency, you may get a different trace file. This is pretty normal. For your case, you may take a look at src/mem/bus.cc and src/sim/eventq_impl.hh as a starting point. Thanks, Amin On Wed, Feb 13, 2013 at 9:38 AM, Negar Miralaei wrote: > Hi All, > > I'm wondering if any

Re: [gem5-users] How to obtain a cycle accurate trace of L1 and L2 cache misses

You can use debug (trace) flags. Try --debug-flags=Cache. This should give you cache misses and their missed addresses as well as more information on cache access. You may want to define your own flag to specifically generate what you need. Thanks, Amin On Tue, Feb 12, 2013 at 8:56 PM, Shivam Ag

Re: [gem5-users] Is it possible to use L2 prefetch with AtomicCPU?

When the memory mode is set to atomic, the prefetcher is NOT activated. As Ali mentioned, you can easily modify the cache_impl.hh to call prefetcher. You need to modify atomicAccess(). Take a look at timingAccess() and see how prefetcher is notified in that function. Thanks, Amin On Wed, Feb 13,

Re: [gem5-users] Running multiple instances of gem5 on a cluster?

Tianyi, If I remember right, the current configs/example/se.py file sets the same frequency for all cores. But you can easily modify that file to set a different frequency to each core. Thanks, Amin On Mon, Feb 4, 2013 at 11:57 PM, Tianyi Wang wrote: > Hi, Erik > > In SE mode, are you able

Re: [gem5-users] fuction getWire()

Hi Ed, Wires are used for inter-stage communications in O3 pipeline. getWire() provides a way to write or read information through wires. Wire and timebuffers are defined in src/cpu/timebuf.hh if you want to know how they work. So the first getWire() setups the wire to write information, and the

Re: [gem5-users] Problem simulating a Cache L3

I didn't read your entire email, but at first glance I noticed that you have two l2caches for a cpu and both are connected to the same master and slave port. Thanks, Amin On Wed, Jan 23, 2013 at 7:32 PM, Rodrigo Reynolds Ramírez < rodrigo.r...@hotmail.com> wrote: > > Hello everyone: > > I need

Re: [gem5-users] Ticks in GEM5

System_.28FS.29_Mode > would be good places. > > Please let me know if you have suggestions. I'll add the explanation later > today after I get your feedback. > > Thanks, > > > Ben > > From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On

Re: [gem5-users] Ticks in GEM5

Do a little bit of search on the forum before posting your question. This has been answered multiple times. A tick is 1ps and your clock cycle could be any number of ticks. For example, a clock cycle of 1ns corresponds to 1000 ticks. Amin On Fri, Dec 21, 2012 at 6:44 PM, Xin Tong wrote: > I se

[gem5-users] DIsabling and enabling stats

There are resetstats and dumpstats magic instructions that are used to dump a separate dump for each ROI. Some programs consist of many ROIs and of course many uninteresting regions. So for those programs calling dumpstats several times would result in a really long stats file. A large stats file i

Re: [gem5-users] cache block size?

In the current classic code, all caches should have the same block size. If you want to have caches with different block sizes, you need to modify the code. I don't know if Ruby supports caches with different line sizes. Thanks, Amin On Fri, Dec 14, 2012 at 12:15 AM, mjkim wrote: > I want to s

Re: [gem5-users] verify cache is writeback

Take a look at src/mem/cache/cache_impl.hh file. Thanks, Amin On Sun, Dec 2, 2012 at 4:02 PM, GiL Vargas wrote: > > Hi, > > Do you know where I can verify that cache is set as writeback?? I read > some posts saying that the cache is writeback but I would like to verify it > in some part of the

Re: [gem5-users] Sum of system.cpu**.num_insts doesn't equal to sim_insts

For IPC, use the number of committed instructions. Amin On Sun, Dec 2, 2012 at 1:50 AM, zhengchl wrote: > Hi, > > Sum of system.cpu**.num_insts doesn't equal to sim_insts? > > sim_insts 1056981309 # Number of instructions > simulated > system.cpu0.num_insts 108073118

Re: [gem5-users] Measuring cache line accesses in direct mapped L1?

The simulator gives you the number of accesses (hits and misses, read/write, etc) to a cache. But if you want to get the number of accesses to each cache line separately, I would guess you need to modify "tags" files. In classic mode, tags files are located in src/mem/cache/tags/*. Thanks, Amin

Re: [gem5-users] Simulating a Blocking Cache

Set both the number of MSHRs and the number of targets per MSHR to 1. If you ONLY set the number of MSHRs to one, then you could have multiple outstanding misses to the same cache line. Amin On Sat, Nov 24, 2012 at 3:30 PM, Nilay Vaish wrote: > On Sat, 24 Nov 2012, pushkar nandkar wrote: > >

[gem5-users] LSQ in O3: Squash instructions when a load packet is rejected by cache

Hi All, In O3 LSQ, when a load packet is not accpeted by L1D (i.e., sendTimingReq() returns false), the pipeline is restarted and the load and all younger instructions are squashed. This causes a lot of instruction squashes when the processor is wide or when cache has a limited number of MSHRs. I

Re: [gem5-users] ARM thumb panic with m5op.h / m5op_arm.S

I had a similar problem with thumb instruction. The patch below (provided by Ali) fixed my problem. I think this should work for you as well. diff -r 839eeb3fcdf8 util/m5/m5op_arm.S --- a/util/m5/m5op_arm.SMon Apr 30 10:23:46 2012 -0500 +++ b/util/m5/m5op_arm.SMon Apr 30 16:50:41

Re: [gem5-users] Cortex-A15 Simulation

I am not an ARM guy, but by looking at the spec I would say that ARM_O3_V7a.py (arm_detailed) is modeled after A9. Thanks, Amin On Mon, Oct 29, 2012 at 6:15 AM, Fernando Endo wrote: > Hi, > > I also wonder what cpu "arm_detailed" correspond to. If it simulates a > real cpu, it can only be A9 or

Re: [gem5-users] Problems with McPAT and gem5

Hi Hongyuan, I wonder if you have made any progress on using the McPAT script ( m5_mcpat.pl) for gem5? I'd like to use that script to automatically get power numbers. So I was wondering if you could share your exprience or your updated script so lazy engineers like me save some time. Thanks, Amin

Re: [gem5-users] Sending information between CPUs

See the inline. Amin On Thu, Oct 11, 2012 at 12:53 PM, David Gloe wrote: > Hello again, > > Does anyone know the function(s) to copy the register file that Amin was > alluding to? > grep copyArchRegs(), copyRegs(), readArchIntReg(), and simialr names. > How about advice on using m5_readfile

Re: [gem5-users] Sending information between CPUs

David, There are functions in gem5 to copy register file from a processor to another. Those functions might help you with what you are tying to do. I don't remember function names off the top of my head though. Thanks, Amin On Tue, Oct 9, 2012 at 10:14 PM, David Gloe wrote: > Hello, > > I woul

Re: [gem5-users] timing access model for dcache ports

t; > ** ** > > Thanks, > > ** ** > > Andreas > > ** ** > > *From:* gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] *On > Behalf Of *Amin Farmahini > *Sent:* 11 September 2012 23:56 > > *To:* gem5 users mailing list

Re: [gem5-users] building Gem5 with cache option on

You are running gem5, not building it! Amin On Sun, Sep 16, 2012 at 2:37 PM, Ardalan Pouya wrote: > Hi everyone , > I built Gem5 with this command : > ./build/X86/gem5.opt --debug-flags=Cache configs/example/fs.py > --kernel="x86_64-vmlinux-2.6.22.9" --caches > and it's more than 8 hours that it

Re: [gem5-users] Instruction execution delay

The instruction delay for ARM O3 is defined in configs/common/O3_ARM_v7a.py . You can do something similar for ALPHA. Amin On Wed, Sep 12, 2012 at 12:48 PM, Jianghao Guo wrote: > Is there any way I can increase execution delay of some instructions? > For example, if I want to increase delay f

Re: [gem5-users] timing access model for dcache ports

ock to >> only allow x bytes per cycle). >> >> The only drawback I can see is that some people might use the higher speed >> to mimic a multi-ported cache. We could always solve that by actually adding >> more ports to the cache if someone really wants to keep t

Re: [gem5-users] timing access model for dcache ports

, 2012 at 10:00 PM, Nilay Vaish wrote: > Amin, you might be correct here. Why don't you investigate this further, > and if you think gem5 should support this, then you can submit a patch > which adds this support to caches. > > -- > Nilay > > Tue, 12 Jun 2012,

[gem5-users] Embedding parameters in ARM psuedo instructions

In ARM, the parameters to m5 pseudo instructions are written to R0, R1, ... registers because pseudo instructions are defined as global functions. I found out that instead of passing parameters to pseudo instructions through architecture registers, it is possible to embed the parameters in the m5 p

Re: [gem5-users] benchmark ROI in gem5

o architectural simulation. SystemTap is >> a profiling tool that uses kprobes; it doesn't really do userspace >> profiling last time I checked. >> >> -Tony >> >> On Fri, Aug 17, 2012 at 1:05 PM, Amin Farmahini wrote: >> >>> Ahn, >>> >

Re: [gem5-users] benchmark ROI in gem5

Ahn, I am not familiar with SystemTap, but I just took a look at its beginners guide and I believe you cannot use this tool for the kind of things Shervin would like to do. This is because "The host system must be the same architecture and running the same distribution of Linux as the target syste

Re: [gem5-users] Changing the latency of ARM Neon instructions

pclass: 4 is defined as FloatAdd in src/cpu/op_class.hh. Thanks, Amin On Thu, Jul 26, 2012 at 8:36 PM, Ali Saidi wrote: > ** > > > > > > On 26.07.2012 19:44, Amin Farmahini wrote: > > Hi, > > I'd like to change the latency of a couple of Neon instructions. I start

[gem5-users] Changing the latency of ARM Neon instructions

Hi, I'd like to change the latency of a couple of Neon instructions. I started with VLD1 instruction which is called ldrNeon in Gem5. This instruction is classified as a "FloatAdd" opClass. So I can modify the latency (opLat) of "FloatAdd" class in O3_ARM_v7a.py file. However, this obviously chang

Re: [gem5-users] ARM mrc instruction in ExecAll trace.

Hi Tony and Ali, I think I find another bug in generateDisassembly() for vmov. I came across this vmov instruction. system.cpu0.fetch: [tid:0]: Instruction is: vmov.w f0, f5, f8 ... system.cpu0 T0 : 0x8978: vmov.w f0, f5, f8 : SimdFloatMisc : D=0x0003 It shows f5 and

[gem5-users] ARM Code Profiling on Gem5

Hi, I would like to profile program code (compiled for ARM ISA) to get function call timings and total cycles taken by each function. I thought one possible option could be gprof. One could use gcc from Code Sourcery to get the instrumented executable file for profiling (-pg) and simulate that exe

Re: [gem5-users] gem5: What should I do to have a non empty m5out/trace.out file after simulation?

;detailed" and "arm_detailed" (I don't know the > difference between them...). > And the parameter "-m 1" is also fine because hello app > finishs before that. > > Thank you very much! > > Regards > > Romulo > > > On Sun, Jul

Re: [gem5-users] gem5: What should I do to have a non empty m5out/trace.out file after simulation?

What is the default cpu-type in gem5? If it is NOT O3 (detailed), then your trace file will remain empty because your specified debug flag (--debug-flags=O3PipeView) do not apply to simple and in-order cpus. Also make sure "-m 1" is right. Amin On Sun, Jul 15, 2012 at 9:06 AM, Romulo

Re: [gem5-users] Question about cache latency in gem5

You haven't enabled L2 cache. Use --l2cache and see the configs/common/CacheConfig.py file. Amin On Mon, Jul 9, 2012 at 12:58 PM, Jinwook Jung wrote: > Hello all, > > ** ** > > I’m running a SPEC2K6 benchmarks in SE mode (gem5.fast) with different > cache latencies, and realized that cache l

Re: [gem5-users] Running my own binaries in gem5

This should help: http://comments.gmane.org/gmane.comp.emulators.m5.users/10990 Amin On Sat, Jun 30, 2012 at 7:16 PM, Nyunyi Tshibangu wrote: > Hi, > I am trying to simulate my personal code written in C++ with gem5 > I started just by compiling "hello.c" that came with gem5 and use it > in

Re: [gem5-users] timing access model for dcache ports

e how you got the trace you posted, but in our > model it's the CPU's responsibility to limit the number of requests to the > cache. > > > > Ali > > > > > > On 12.06.2012 15:40, Amin Farmahini wrote: > > I only modified the code in cpu side and not

Re: [gem5-users] timing access model for dcache ports

I only modified the code in cpu side and not the cache. And CPU::DcachePort::recvTiming() is called when the l1 cache has made a response packet ready. I would guess the same behavior can be seen in O3 cpu, because what I am doing is similar to LSQ implementation in O3. I totally agree that this sh

[gem5-users] timing access model for dcache ports

Hi, I am doing some analysis with the Timing access model for dcache ports and I am seeing weird behavior that does not make sense to me. Similar to the DcachePort class in Timing and O3 cpus, I have a CPU::DcachePort::recvTiming() function that processes timing packets received by DcachePort in c

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