I have a question about the stats generated in classic memory model. I realized that overall_access is always the sum of ReadReq_accesses and ReadExReq_accesses.
system.l2.ReadReq_accesses::total 3816827 system.l2.Writeback_accesses::total 5433149 system.l2.UpgradeReq_accesses::total 656 system.l2.ReadExReq_accesses::total 4813881 system.l2.overall_accesses::total 8630708 As far as I know ReadReq reads the cache line and data is sent back via ReadResp. ReadExReq reads the cache line, invalidates it, and data is sent back via ReadExResp. Writeback writes a cache line when a dirty line is evicted from a higher level cache (e.g. L1). So I think overall_accesses should be the sum of ReadReq_accesses, ReadExReq_accesses, and Writeback_accesses. Any thoughts? My architecture: two cores with private L1s and a shared L2; ARM; SE; classic memory Thanks, Amin
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