In ARM, the parameters to m5 pseudo instructions are written to R0, R1, ...
registers because pseudo instructions are defined as global functions. I
found out that instead of passing parameters to pseudo instructions through
architecture registers, it is possible to embed the parameters in the m5
pseudo instructions. For example in ARM, those parameters can be embedded
in ra, rb, coproc bits. The reason is that those bits are not used at all.
Here is how m5 pseudo instructions are defined:
#define INST(op, ra, rb, func) \
.long (((op) << 24) | ((func) << 16) | ((ra) << 12) | (0x1 << 8) |
(0x1 << 4) | (rb))
/* m5ops m5func ra coproc
1 op=1 rb */
So clearly ra, rb, etc can be used to pass parameters and even define new
instructions with the same opcode (ie, with the same m5ops and m5func). If
I am not mistaken to make use of ra and rb, ARM ISA should be modified a
little bit and I think arch/arm/isa/formats/m5ops.isa and
arch/arm/isa/decoder/arm.isa files have to be edited. However, I am not
sure how to to make those changes. If you have some idea about it, I would
be grateful if you could share it.
Thanks,
Amin
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