Hi, After updating to changeset 10338 (condition code registers for ARM), I observed some (relatively significant) performance improvement. On a particular workload which I usually check when I update gem5, the execution time improves by 9%. It seems like the perf improvement is caused by having more registers as FullRegisterEvents goes down by 25%, which makes sense. While I understand that introducing CC registers could improve performance, I did not expect adding half a dozen CC registers could have such a huge perf impact. Any thoughts?
ARM, SE, O3 4-way, 128 int registers Thanks, Amin
_______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
