[Discuss-gnuradio] FPGA image build incorect size

I have been following the instruction for Getting Started with RFNOC Development. I have made it to the point of generating a custom FPGA image with the following command ./uhd_image_builder.py window fft -d x310 -t X310_RFNOC_HG -m 5 --fill-with-fifos with the following status on completion

Re: [Discuss-gnuradio] FPGA compatibility

Thanks a lot Juan El sáb., 18 ago. 2018 11:45, Müller, Marcus (CEL) escribió: > The Ubuntu gnuradio package does install libgnuradio-uhd with it, and > that in turn installs UHD. > > So, this was unnecessary! > > Also, it can't work: software must be run with the library versions > that it was

Re: [Discuss-gnuradio] FPGA compatibility

The Ubuntu gnuradio package does install libgnuradio-uhd with it, and that in turn installs UHD. So, this was unnecessary! Also, it can't work: software must be run with the library versions that it was linked against, not some other random version. So, what you've done is exactly what you're obs

Re: [Discuss-gnuradio] FPGA compatibility

I install gqrx from the ppa, and this install directly gnuradio but it seems to me that the uhd driver is not installed, them I instal the ppa fron ettus from this page https://files.ettus.com/manual/page_install.html and I load: libuhd-dev, libuhd003, and uhd-host and run: uhd_images_downloader w

Re: [Discuss-gnuradio] FPGA compatibility

Hi Juan, You're right; that message does mean the FPGA image is incompatible with your UHD installation. You'll want to run the uhd_images_downloader that came with your GNURadio installation. That should overwrite the images stored on your host to a set of images that are compatible with the vers

[Discuss-gnuradio] FPGA compatibility

I have reinstaled the uhd driver an the FPGA images for my B210, and suddently this error appears when I try to run my usual GNUradio programs RuntimeError: RuntimeError: Expected FPGA compatibility number 14, but got 15: The FPGA build is not compatible with the host code build. It seems that th

Re: [Discuss-gnuradio] FPGA code generation using gnu radio

Dear Atif, _Please_ try to keep your replies on the mailing list. On Mon, 2017-11-06 at 01:08 -0800, Atif Javed wrote: > That dosen't relate with FPGA code problem Why then did you reply to your FPGA thread? > Basically i want to take control of usrp parameters like Bandwidth, > Sampling Rate

Re: [Discuss-gnuradio] FPGA code generation using gnu radio

Dear Atif, this was a step in the right direction, but not nearly enough info for us to help you. Remember, as said in my reply[1] to your original mail, which you seem to have ignored: * Problem statement, as exact as possible. /What problem are you trying to solve with your block?/ * Ap

Re: [Discuss-gnuradio] FPGA code generation using gnu radio

hello all I am trying to create my own UHD block in gnu radio for this i use cc files of already available module but i can't be able to do it. I have a basic knowledge of OOT blocks and have able to create blocks using this technique. can you please list the steps for this purpose. Any help in t

Re: [Discuss-gnuradio] FPGA code generation using gnu radio

Dear Atif, no, not directly. GNU Radio is software, FPGAs are hardware. Generally, how do you expect us to answer such quite frankly obviously immensely broad questions? It's always better to ask a precise question that describes the problem (and that: exactly), then to ask about something la

[Discuss-gnuradio] FPGA code generation using gnu radio

Is it possible to generate FPGA code using gnu radio if so than please guide me. ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org https://lists.gnu.org/mailman/listinfo/discuss-gnuradio

Re: [Discuss-gnuradio] FPGA Images on Ettus E310

Hi John, they are on the SD Card just because the default method of getting them downloads a whole bunch of images. An FPGA image is 100% specific to exactly the FPGA and connections. The N210's FPGA and the Zynq's PL aren't even similar; this can't work out, you can't even successfully load such

[Discuss-gnuradio] FPGA Images on Ettus E310

Hello, all. In the /usr/share/uhd/images directory on the ARMv7 processor (p/o of the E310 and running Xilinx Linux) there are a number of FPGA images for ostensibly other architectures besides the E310. If another of these, say one of the several ones for an N210 device are loaded into the E

Re: [Discuss-gnuradio] FPGA update

On 03/23/2016 03:32 PM, Diyar Muhammed wrote: Dear All, I have got new usrp x310 with UBX160 daughter board, I assembled the usrp, but when I run the uhd_usrp_probe --args addr=192.168.10.2 there is a UHD Warning: /X300 unknown product code in EEPROM:30818/ /Error: RuntimeError: Expected firm

[Discuss-gnuradio] FPGA update

Dear All, I have got new usrp x310 with UBX160 daughter board, I assembled the usrp, but when I run the uhd_usrp_probe --args addr=192.168.10.2 there is a UHD Warning: *X300 unknown product code in EEPROM:30818* *Error: RuntimeError: Expected firmware compatibility number 3.0, but got 4.0:* *The f

[Discuss-gnuradio] FPGA compatibility number X310

Hello, I am setting up a new computer to talk to a x310 previously used on another system. I installed on this computer gnuradio and uhd on ubuntu 14.04 from the latest (yesterday) build-gnuradio script from Marcus Leech. All works fine with a N210. However, with a usrp x310 on standard ethern

Re: [Discuss-gnuradio] FPGA image burning error

Hi Thanks for the suggestion. I could burn the images finally after renaming the file to u2plus_usrp_n200_r4_fpga.bin and using ./usrp_n2xx_net_burner_gui.py --dont-check-rev (It was showing error even with u2plus_r4.bin or u2plus_n200_r4.bin) Amy On 07/24/2013 12:48 PM, Amy Kumar wrote:

Re: [Discuss-gnuradio] FPGA image burning error

On 07/24/2013 12:48 PM, Amy Kumar wrote: Hi I made a change in the u2plus_core.v and generated a new bin file using: make -f Makefile.N200R4 bin When I try burning the new FPGA image to USRP N200 R4, I get the following error: 'Error: incorrect FPGA image version.Please use the correct image f

[Discuss-gnuradio] FPGA image burning error

Hi I made a change in the u2plus_core.v and generated a new bin file using: make -f Makefile.N200R4 bin When I try burning the new FPGA image to USRP N200 R4, I get the following error: 'Error: incorrect FPGA image version.Please use the correct image for device n200_r4' I think the revision I'v

Re: [Discuss-gnuradio] FPGA code for N210

https://github.com/EttusResearch/uhd Under fpga/usrp2/top/N2x0 -Ian On Jul 16, 2013, at 10:10 PM, Sam mite wrote: > Hi list, > > I want to compile USRP N210 FPGA code. From where I can get the latest fpga > code for USRP N210 ? Please provide the link. Any help will be appreciated. > > --

[Discuss-gnuradio] FPGA code for N210

Hi list, I want to compile USRP N210 FPGA code. From where I can get the latest fpga code for USRP N210 ? Please provide the link. Any help will be appreciated. -- Sam ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org https://lists.gnu.org/mai

Re: [Discuss-gnuradio] FPGA time

Hello, Sorry for the lack of response, I was on vacation. We actually managed to fix most of our problems, mostly due to hardware setup issues. Thank you for your help! On Wed, Aug 29, 2012 at 3:18 PM, wrote: > ** > > On 29 Aug 2012 15:13, Josh Blum wrote: > > On 08/28/2012 03:24 PM, Anisha Goru

Re: [Discuss-gnuradio] FPGA time

On 29 Aug 2012 15:13, Josh Blum wrote: > On 08/28/2012 03:24 PM, Anisha Gorur wrote: > >> Sorry for the confusion. We are trying to synchronize 3 usrps for collect. The devices seem to be time aligned in that the samples are timestamped with the same metadata, so we believed that synchronizat

Re: [Discuss-gnuradio] FPGA time

On 08/28/2012 03:24 PM, Anisha Gorur wrote: > Sorry for the confusion. We are trying to synchronize 3 usrps for collect. > The devices seem to be time aligned in that the samples are timestamped > with the same metadata, so we believed that synchronization had been > achieved. However, when the d

Re: [Discuss-gnuradio] FPGA time

Sorry for the confusion. We are trying to synchronize 3 usrps for collect. The devices seem to be time aligned in that the samples are timestamped with the same metadata, so we believed that synchronization had been achieved. However, when the data collected from the usrps was correlated, samples t

Re: [Discuss-gnuradio] FPGA time

On 08/28/2012 01:39 PM, Anisha Gorur wrote: > Thats actually what we are using, however, when printing out the tick > count, we randomly, and only sometimes, see a jump of about 30 ticks, and > if each tick is 10ns, that is a huge 300ns jump. Do you know why this could > be happening? > I'm ver

Re: [Discuss-gnuradio] FPGA time

Thats actually what we are using, however, when printing out the tick count, we randomly, and only sometimes, see a jump of about 30 ticks, and if each tick is 10ns, that is a huge 300ns jump. Do you know why this could be happening? We are using gpsdo's as both a time and clock reference, though

Re: [Discuss-gnuradio] FPGA time

On 08/28/2012 12:03 PM, Anisha Gorur wrote: > Hello, > We've been having some trouble with the synchronizing aspects of our > project. What we want is the exact same time as the FPGA tick counter, not > a time_spec_t representation of time. Where can we get access to that? > Thanks! > -Anisha >

[Discuss-gnuradio] FPGA time

Hello, We've been having some trouble with the synchronizing aspects of our project. What we want is the exact same time as the FPGA tick counter, not a time_spec_t representation of time. Where can we get access to that? Thanks! -Anisha ___ Discuss-gnura

[Discuss-gnuradio] fpga halfband filter

Dear everyone: In the FPGA code of halfband_decim,v of USRP1, it has a input strobe_in, which indates a new data comes. Strobe_in is determined by the decimation rate. For example if we decimate by 6 we write to the register FR_DECIM_RATE 6/2-1=2 and strobe_in comes high every 3 clocks.

Re: [Discuss-gnuradio] FPGA mo

On Sat, May 28, 2011 at 21:04, Marcus D. Leech wrote: >> Hi all, >> >> I'm not sure whether to post this to GnuRadio or to USRP-users, so I >> post it here. >> >> We've started a project to implement a custom SDR hardware (which we >> plan to open-source later) and we want to reuse as much of USRP

Re: [Discuss-gnuradio] FPGA mo

Hi all, I'm not sure whether to post this to GnuRadio or to USRP-users, so I post it here. We've started a project to implement a custom SDR hardware (which we plan to open-source later) and we want to reuse as much of USRP FPGA code as possible. But it will require a good deal of customization

[Discuss-gnuradio] FPGA mo

Hi all, I'm not sure whether to post this to GnuRadio or to USRP-users, so I post it here. We've started a project to implement a custom SDR hardware (which we plan to open-source later) and we want to reuse as much of USRP FPGA code as possible. But it will require a good deal of customization a

[Discuss-gnuradio] FPGA Security

Has anyone else seen this? fpgavirus.pdf Justin ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio

Re: [Discuss-gnuradio] FPGA usage in USRP E100

Hi Matt, On Mon, Jan 24, 2011 at 21:42, Matt Ettus wrote: > On 01/24/2011 10:30 AM, Alexander Chemeris wrote: >> Is there any high-level description of what processing is done in FPGA >> in E100 and is there any optional blocks which can be removed? I see >> that even aeMB is present in the proje

Re: [Discuss-gnuradio] FPGA usage in USRP E100

On 01/24/2011 10:30 AM, Alexander Chemeris wrote: Hi all, Is there any high-level description of what processing is done in FPGA in E100 and is there any optional blocks which can be removed? I see that even aeMB is present in the project - is it used or it is not compiled in? There is no aeMB

[Discuss-gnuradio] FPGA usage in USRP E100

Hi all, Is there any high-level description of what processing is done in FPGA in E100 and is there any optional blocks which can be removed? I see that even aeMB is present in the project - is it used or it is not compiled in? I need to understand how much resource is left for custom DSP process

Re: [Discuss-gnuradio] FPGA and Firmware of USRP2

On 12/27/2010 12:39 AM, 陈敏 wrote: > Dear all,I have downloaded the fpga code of USRP2 from: > git://ettus.sourcerepo.com/ettus/uhd.git and compile with ISE10.1 > like this: cd uhd\fpga\usrp2\top\u2_rev3 make but the output file in > uhd\fpga\usrp2\top\u2_rev3\build is 0 byte.Is there anything el

[Discuss-gnuradio] FPGA and Firmware of USRP2

Dear all,I have downloaded the fpga code of USRP2 from: git://ettus.sourcerepo.com/ettus/uhd.git and compile with ISE10.1 like this: cd uhd\fpga\usrp2\top\u2_rev3 make but the output file in uhd\fpga\usrp2\top\u2_rev3\build is 0 byte.Is there anything else I sould do?Is there any difference betwee

Re: [Discuss-gnuradio] FPGA code for USRP2

git clone git://git.ettus.com/ettus/fpga.git works for me. Perhaps you are behind a firewall that blocks the git protocol? -Josh On 02/12/2010 08:40 AM, senlin peng wrote: Hi All, I need to make some modifications on the USRP2 board. It seems I cannot download the code from: git clone git://g

[Discuss-gnuradio] FPGA code for USRP2

Hi All, I need to make some modifications on the USRP2 board. It seems I cannot download the code from: git clone git://git.ettus.com/ettus/fpga.git. I don't know why. Does anyone know where I can get the Verilog codes and rebuild them? -- Best Regards! ___

[Discuss-gnuradio] fpga verilog question

I am trying to transmit an ASK packet from the usrp fpga(verilog) without using usb data. I cant figure out where should I put the I-q data in verilog. does anyone know what clock(rate) is used to transfer it to ad9862? I observed that the tx_sync signal decides whether data on tx_a[13..0] is

[Discuss-gnuradio] FPGA pic link down

Just an FYI that the link http://img179.imageshack.us/img179/8650/usrpblockdkmyg9.jpg on the wiki is down. -- Newell ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio

Re: [Discuss-gnuradio] FPGA "headroom" in USRP2

On Mon, Feb 9, 2009 at 10:36 PM, Johnathan Corgan wrote: > On Mon, Feb 9, 2009 at 6:25 PM, Marcus D. Leech wrote: > >> Is there room in the USRP2 for building a 2048 lag autocorrelator with 1 >> or 2-bit sampling? > > Most likely. I did the investigation to implement a fully pipelined > 2048 poi

Re: [Discuss-gnuradio] FPGA "headroom" in USRP2

On Mon, Feb 9, 2009 at 6:25 PM, Marcus D. Leech wrote: > Is there room in the USRP2 for building a 2048 lag autocorrelator with 1 > or 2-bit sampling? Most likely. I did the investigation to implement a fully pipelined 2048 point FFT with 16-bit I/Q samples using the Xilinx core generator softw

[Discuss-gnuradio] FPGA "headroom" in USRP2

Is there room in the USRP2 for building a 2048 lag autocorrelator with 1 or 2-bit sampling? -- Marcus Leech Principal Investigator, Shirleys Bay Radio Astronomy Consortium http://www.sbrac.org ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.or

Re: [Discuss-gnuradio] FPGA Modeling in MATLAB/Octave

On Wed, Oct 1, 2008 at 3:43 PM, Eric Blossom <[EMAIL PROTECTED]> wrote: > On Wed, Oct 01, 2008 at 02:53:40PM -0400, Kyle Pearson wrote: >> I'm looking to model the rx_chain of the USRP using MATLAB's fixed >> point toolbox and I'm wondering if anyone has tried this yet in MATLAB >> or Octave. >> >>

Re: [Discuss-gnuradio] FPGA Modeling in MATLAB/Octave

On Wed, Oct 1, 2008 at 3:43 PM, Eric Blossom <[EMAIL PROTECTED]> wrote: > Excuse me if this is totally off the wall, but since if you run the > verilog under a simulator (e.g., icarus), it will generate traces that > give you all the state, on every clock. What's to model? Verilog simulators can

Re: [Discuss-gnuradio] FPGA Modeling in MATLAB/Octave

On Wed, Oct 01, 2008 at 02:53:40PM -0400, Kyle Pearson wrote: > I'm looking to model the rx_chain of the USRP using MATLAB's fixed > point toolbox and I'm wondering if anyone has tried this yet in MATLAB > or Octave. > > Thanks, > Kyle Excuse me if this is totally off the wall, but since if you r

RE: [Discuss-gnuradio] FPGA Modeling in MATLAB/Octave

dead" -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Kyle Pearson Sent: Wednesday, October 01, 2008 2:54 PM To: Gnu radio Mailing list Subject: [Discuss-gnuradio] FPGA Modeling in MATLAB/Octave I'm looking to model the rx_chain of the USRP using

[Discuss-gnuradio] FPGA Modeling in MATLAB/Octave

I'm looking to model the rx_chain of the USRP using MATLAB's fixed point toolbox and I'm wondering if anyone has tried this yet in MATLAB or Octave. Thanks, Kyle ___ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/li

RE: [Discuss-gnuradio] FPGA / new rx_buffer_inband

> -Original Message- > From: Brian Padalino [mailto:[EMAIL PROTECTED] > If it's coming from two different parts of the chip with two > independent reset signals, then yes there is always suspicion that > they are unaligned. I didn't realize there were different resets. It should be change

Re: [Discuss-gnuradio] FPGA / new rx_buffer_inband

Eric Schneider wrote: -Original Message- From: George Nychis [mailto:[EMAIL PROTECTED] I'm not sure what code you started from, Eric S. ... I had mentioned I had some fixes in my own developer branch, one of which was making sure there was only 1 counter: http://gnuradio.org/trac/change

RE: [Discuss-gnuradio] FPGA / new rx_buffer_inband

> -Original Message- > From: George Nychis [mailto:[EMAIL PROTECTED] > I'm not sure what code you started from, Eric S. ... I had mentioned I > had some fixes in my own developer branch, one of which was making sure > there was only 1 counter: > http://gnuradio.org/trac/changeset/8987 > htt

RE: [Discuss-gnuradio] FPGA / new rx_buffer_inband

> -Original Message- > From: George Nychis [mailto:[EMAIL PROTECTED] > > Just going to chime in here with nothing really too important, because > this isn't really my area. But, I am trying to follow discussion here, > and I appreciate you working on this Eric. > > As for your segmentati

Re: [Discuss-gnuradio] FPGA / new rx_buffer_inband

Eric Blossom wrote: On Mon, Sep 08, 2008 at 04:49:23PM -0400, Brian Padalino wrote: Problems arise when you want to ensure your FIFO is not full and not empty. As a message passing mechanism, it works pretty well as just a DPRAM. As the FIFO, there are counters involved which can cause timin

Re: [Discuss-gnuradio] FPGA / new rx_buffer_inband

On Mon, Sep 08, 2008 at 04:49:23PM -0400, Brian Padalino wrote: > > Problems arise when you want to ensure your FIFO is not full and not > empty. As a message passing mechanism, it works pretty well as just a > DPRAM. As the FIFO, there are counters involved which can cause > timing issues when

Re: [Discuss-gnuradio] FPGA / new rx_buffer_inband

Just going to chime in here with nothing really too important, because this isn't really my area. But, I am trying to follow discussion here, and I appreciate you working on this Eric. As for your segmentation faults, if you e-mail me your RBF where you're getting these, I can poke at why you

Re: [Discuss-gnuradio] FPGA / new rx_buffer_inband

On Mon, Sep 8, 2008 at 4:26 PM, Eric Schneider <[EMAIL PROTECTED]> wrote: > I have no direct knowledge regarding this, but from reading the Cyclone > datasheets it seems like the MK4 blocks natively support two fully > independent asynchronous r/w ports. Where would the problems arise? A > clock

RE: [Discuss-gnuradio] FPGA / new rx_buffer_inband

> -Original Message- > From: Brian Padalino [mailto:[EMAIL PROTECTED] > > No. It just seems silly to have a hard wrapper (fifo_1kx16_dc_la) for > a generic wrapper (dcfifo). It would be nice if there was an > identification of the different FIFOs and made those aspects generics > to a t

Re: [Discuss-gnuradio] FPGA / new rx_buffer_inband

On Mon, Sep 8, 2008 at 2:27 PM, Eric Schneider <[EMAIL PROTECTED]> wrote: > Thanks for the input Brian. A few comments inline. > > Are you talking about not using the megacells at all? I see your point, but > I don't see it as a high priority. No. It just seems silly to have a hard wrapper (fif

RE: [Discuss-gnuradio] FPGA / new rx_buffer_inband

Thanks for the input Brian. A few comments inline. > -Original Message- > From: Brian Padalino [mailto:[EMAIL PROTECTED] > Sent: Monday, September 08, 2008 7:58 AM > To: Eric Schneider > Cc: discuss-gnuradio@gnu.org > Subject: Re: [Discuss-gnuradio] FPGA / new rx_buf

Re: [Discuss-gnuradio] FPGA / new rx_buffer_inband

On Sun, Sep 7, 2008 at 6:43 PM, Eric Schneider <[EMAIL PROTECTED]> wrote: > On that note, I'd like to get refactoring suggestions. I don't like all the different memory megacells. Wrap the altsyncram/fifo with the generics you require and pass those in using the same module underneath. It reduce

RE: [Discuss-gnuradio] FPGA / new rx_buffer_inband

> -Original Message- > From: Brian Padalino [mailto:[EMAIL PROTECTED] > Sent: Sunday, September 07, 2008 3:03 PM > I am disappointed by the prioritization scheme for the channels and > would have rather seen a more fair round-robin approach instead of a > priority encoder. Man, tough cro

Re: [Discuss-gnuradio] FPGA / new rx_buffer_inband

On Sun, Sep 7, 2008 at 4:47 PM, Eric Schneider <[EMAIL PROTECTED]> wrote: > They were from the 1 channel build. > > Here is a snippet from inband_2rxhb_2tx.rbf: > > ch: 0 s: 965745 delta: 8064 > ch: 1 s: 965745 delta: 8064 > ch: 0 s: 973809 delta: 8064 > ch: 1 s: 973809

RE: [Discuss-gnuradio] FPGA / new rx_buffer_inband

> -Original Message- > From: Brian Padalino [mailto:[EMAIL PROTECTED] > Sent: Sunday, September 07, 2008 7:21 AM > > Were these results for the 2 channel mode? > > What is the size difference within the USRP when using 2 channels? Is > it significant or pretty insignificant? They were f

Re: [Discuss-gnuradio] FPGA / new rx_buffer_inband

On Sun, Sep 7, 2008 at 4:28 AM, Eric Schneider <[EMAIL PROTECTED]> wrote: > For those interested, > > > > I've committed my changes to the inband RX buffering subsystem. It is > available at: > > > > http://gnuradio.org/svn/gnuradio/branches/developers/ets/inband/usrp/fpga > > > > Source only at t

[Discuss-gnuradio] FPGA / new rx_buffer_inband

For those interested, I've committed my changes to the inband RX buffering subsystem. It is available at: http://gnuradio.org/svn/gnuradio/branches/developers/ets/inband/usrp/fpga Source only at the moment, I'm not sure of the policy for RBFs in dev branches. Caveat emptor. The m

[Discuss-gnuradio] FPGA processing

Hi Gnu Radio People, I played a little with the Fedora8/64 gnuradio without currently having money to get the Hardware Unit, so I'd hope I could use my existing spartan 3(e) boards for the main connection with a PC, but that currently seems not to be the case. Of course the AD (DA) electronics ar

Re: [Discuss-gnuradio] FPGA sample timestamps

Hi Roshan, With the in-band signaling implementation we have added timestamps to all data across the USB bus. You can find the new packet structure here: http://gnuradio.org/trac/browser/gnuradio/trunk/usrp/doc/inband-signaling-usb I'm not sure what kind of application you want to create or u

[Discuss-gnuradio] FPGA sample timestamps

Hi all, For one of our applications we think we need timestamps for some or all samples coming across the USB bus. I know there was some mention of this a while ago on the list, but I didn't find an open ticket on Trac. Obviously we would submit our changes back to gnuradio for inclusion in

Re: [Discuss-gnuradio] FPGA firmware

On Tue, Aug 28, 2007 at 11:02:25PM +0200, Dominik Auras wrote: > Hi! > > Am I right to state that the fpga firmware is configured as followed: > > Tx chain (0 to 2 possible) > - NCO fine+coarse on Analog Devices Chip > - low-pass 4x interpolation on AD-Chip > - CIC interpolation filters, separate

[Discuss-gnuradio] FPGA firmware

Hi! Am I right to state that the fpga firmware is configured as followed: Tx chain (0 to 2 possible) - NCO fine+coarse on Analog Devices Chip - low-pass 4x interpolation on AD-Chip - CIC interpolation filters, separate for I- and Q-Data Especially: Cordic turned off, internal DUC (duc.v) turned

[Discuss-gnuradio] FPGA original firmware problems

Hello list, First I apologise for posting in the Recovering x(t) from IQ samples thread, please delete my post there if possible. I also removed my old account from the list and created this new one. I have recently changed the USRP clock with an external PLL. Then I used the previously precomp

Re: [Discuss-gnuradio] FPGA .rbf file

On Wed, Aug 01, 2007 at 03:34:56PM -0700, Michael P Buettner wrote: > >On Tue, May 08, 2007 at 10:59:33AM -0400, Steven Clark wrote: > >> Hi all- > >> > >> I noticed that both the usrp.source and usrp.sink blocks have the > >ability to > >> specify the .rbf bit file for the FPGA. > >> > >> Does

Re: [Discuss-gnuradio] FPGA .rbf file

On Tue, May 08, 2007 at 10:59:33AM -0400, Steven Clark wrote: > Hi all- > > I noticed that both the usrp.source and usrp.sink blocks have the ability to > specify the .rbf bit file for the FPGA. > > Does that mean that in the following: > > > self.usrp_in = usrp.source_c (fpga_filename="file_

Re: [Discuss-gnuradio] FPGA Modifications for a Continuous Carrier?

looked at a number of examples that have no overruns using the normal .rbf file, and when I swap in my .rbf the continuous overruns invariably result. It appears that no data is arriving at the host, and the received samples are stopped completely somewhere. Does anyone have any insight as t

Re: [Discuss-gnuradio] FPGA Modifications for a Continuous Carrier?

On Tue, 24 Jul 2007, Brian Padalino wrote: My question is, would it be possible to modify the FPGA so that the default behavior is to transmit the carrier until it receives buffers for transmit? This should reduce the latency by using the USB half duplex, keeping the TX buffers empty which

Re: [Discuss-gnuradio] FPGA Modifications for a Continuous Carrier?

On 7/24/07, Michael P Buettner <[EMAIL PROTECTED]> wrote: Thanks Brian, that was just what I was looking for. I've now enough to dig into anyway, and we'll see what happens. Are there any current testbenches? The only testbench I can find is full_chip which is defunct. Whoops - I gues

Re: [Discuss-gnuradio] FPGA Modifications for a Continuous Carrier?

On Tue, 24 Jul 2007, Brian Padalino wrote: You can see how at line 72 there is a case statement and if the TX FIFO is empty, the values are set to be zero. I am not 100% sure, but I believe if you change these values to be non-zero you will get a carrier to come out. Moreover, once the TX FIF

Re: [Discuss-gnuradio] FPGA Modifications for a Continuous Carrier?

On 7/24/07, Michael P Buettner <[EMAIL PROTECTED]> wrote: Hello folks. I am currently looking at using the USRP for interaction with RFID tags. The crux of the problem is that I need to transmit a continuous carrier wave to power the tag, but I also need very low latency with respect to receiv

[Discuss-gnuradio] FPGA Modifications for a Continuous Carrier?

Hello folks. I am currently looking at using the USRP for interaction with RFID tags. The crux of the problem is that I need to transmit a continuous carrier wave to power the tag, but I also need very low latency with respect to receiving a tag signal and responding to that signal (< 500us.

Re: [Discuss-gnuradio] FPGA Gain?

Eric Cottrell wrote: >> The ADC has a programmable gain stage prior to sampling. Could it >> be that one you are thinking of? > > It must be. I thought there was a digital amplifier implemented in > the FPGA. The USRP motherboard AD9862 ADC has a programmable analog voltage gain range from 0 to

Re: [Discuss-gnuradio] FPGA Gain?

- Start Original Message - Sent: Wed, 11 Jul 2007 12:38:41 +0200 From: "Trond Danielsen" <[EMAIL PROTECTED]> To: discuss-gnuradio@gnu.org Subject: Re: [Discuss-gnuradio] FPGA Gain? > 2007/7/10, Eric Cottrell <[EMAIL PROTECTED]>: > > Hello, > > > >

Re: [Discuss-gnuradio] FPGA Gain?

2007/7/10, Eric Cottrell <[EMAIL PROTECTED]>: Hello, The LFRX daughterboard on the USRP has 20 dB of gain. I seem to remember that 10 dB of that gain is from the FPGA. I assume that this gain is after the ADC? If so, is it really useful? I relate digital gain to zoom on a digital camera.

[Discuss-gnuradio] FPGA Gain?

Hello, The LFRX daughterboard on the USRP has 20 dB of gain. I seem to remember that 10 dB of that gain is from the FPGA. I assume that this gain is after the ADC? If so, is it really useful? I relate digital gain to zoom on a digital camera. The analog gain is the optical zoom and the dig

Re: [Discuss-gnuradio] FPGA in USRP

2007/6/15, Achilleas Anastasopoulos <[EMAIL PROTECTED]>: Dear Mande here is an application that requires significant FPGA functionality: try to design the first stages of a spread-spectrum receiver, ie, the part of the receiver that does pn code acquisition (and tracking). This is a demanding t

Re: [Discuss-gnuradio] FPGA in USRP

Dear Mande here is an application that requires significant FPGA functionality: try to design the first stages of a spread-spectrum receiver, ie, the part of the receiver that does pn code acquisition (and tracking). This is a demanding task that needs to be performed on hardware. Once code acq

Re: [Discuss-gnuradio] FPGA in USRP

On 6/14/07, S Mande <[EMAIL PROTECTED]> wrote: Hi All, I have worked with VHDL for 3 years and would want to make use my knowledge to do some research in Software defined Radio. I have a very different problem from most of the other postings. I am actually looking for a 'problem'. For the

[Discuss-gnuradio] FPGA in USRP

Hi All, I have worked with VHDL for 3 years and would want to make use my knowledge to do some research in Software defined Radio. I have a very different problem from most of the other postings. I am actually looking for a 'problem'. For the past one month I have been Googling to see the resea

Re: [Discuss-gnuradio] FPGA .rbf file

On Tue, May 08, 2007 at 10:59:33AM -0400, Steven Clark wrote: > Hi all- > > I noticed that both the usrp.source and usrp.sink blocks have the ability to > specify the .rbf bit file for the FPGA. > > Does that mean that in the following: > > > self.usrp_in = usrp.source_c (fpga_filename="file_A.

[Discuss-gnuradio] FPGA .rbf file

Hi all- I noticed that both the usrp.source and usrp.sink blocks have the ability to specify the .rbf bit file for the FPGA. Does that mean that in the following: self.usrp_in = usrp.source_c (fpga_filename="file_A.rbf") self.usrp_out = usrp.sink_c (fpga_filename="file_B.rbf") Only file_B ha

Re: [Discuss-gnuradio] FPGA

Kuntal wrote: > Hello, > > Is anyone of you working fulltime with the FPGA? I want to ask a few > questions. I suspect you mean the FPGA on the usrp. > Because I hardly find any documentation on GnuWiki on that or I hardly get > any replies to my posts on the FPGA. This might be because you questi

[Discuss-gnuradio] FPGA

Hello, Is anyone of you working fulltime with the FPGA? I want to ask a few questions. Because I hardly find any documentation on GnuWiki on that or I hardly get any replies to my posts on the FPGA. Thanks a lot. Kuntal -- View this message in context: http://www.nabble.com/FPGA-tf3606449.ht

Re: [Discuss-gnuradio] FPGA Questions

Eric Blossom wrote: On Sat, Feb 24, 2007 at 05:13:22PM -0500, Brian Padalino wrote: On 2/24/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote: Hi all, I have dived into the fpga code and I have now much clearer picture of what is going on, but also much more questions :) The Tx CORDIC i

Re: [Discuss-gnuradio] FPGA mods

On Mon, Feb 26, 2007 at 03:49:19PM -0800, Dan Halperin wrote: > Hi, > > I'm working on FPGA mods to push a little bit of work off of the > computer onto the USRP's FPGA. If I understand correctly, the right way > to do what I want is to create a new config file (e.g. a modification of > usrp_st

[Discuss-gnuradio] FPGA mods

Hi, I'm working on FPGA mods to push a little bit of work off of the computer onto the USRP's FPGA. If I understand correctly, the right way to do what I want is to create a new config file (e.g. a modification of usrp_std_config_2rxhb_2tx.vh) with my changes in the defines. First, the comme

Re: [Discuss-gnuradio] FPGA Questions

On Sat, Feb 24, 2007 at 05:13:22PM -0500, Brian Padalino wrote: > On 2/24/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote: > >Hi all, > > > >I have dived into the fpga code and I have now much clearer picture of > >what is going on, but also much more questions :) > > > >The Tx CORDIC is disabled i

Re: [Discuss-gnuradio] FPGA Questions

On 2/24/07, Thibaud Hottelier <[EMAIL PROTECTED]> wrote: Hi all, I have dived into the fpga code and I have now much clearer picture of what is going on, but also much more questions :) The Tx CORDIC is disabled in the code I checked out. Why? I could be wrong, but I think the TX CORDIC is di

[Discuss-gnuradio] FPGA Questions

Hi all, I have dived into the fpga code and I have now much clearer picture of what is going on, but also much more questions :) The Tx CORDIC is disabled in the code I checked out. Why? I have failed to find a description of how to control the AD9862 chip on the Analog Device web site. Where is

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