Eric Cottrell wrote:

>> The ADC has a programmable gain stage prior to sampling. Could it
>> be that one you are thinking of?
> 
> It must be.  I thought there was a digital amplifier implemented in
> the FPGA.

The USRP motherboard AD9862 ADC has a programmable analog voltage gain
range from 0 to 20 dB.  This results in a full scale input voltage of 2V
peak-to-peak at 0 dB down to 0.2V peak-to-peak at 20 dB.  The various
receiver daughterboards of course have their own gain ahead of this.

-- 
Johnathan Corgan
Corgan Enterprises LLC
http://corganenterprises.com


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