> -----Original Message-----
> From: Brian Padalino [mailto:[EMAIL PROTECTED]
> If it's coming from two different parts of the chip with two
> independent reset signals, then yes there is always suspicion that
> they are unaligned.

I didn't realize there were different resets.  It should be changed anyway.

> Are you sure you're currently meeting timing?

No :-)

But the previous inband build reported the same master_clock warnings during
synthesis.

Most of my logic is on usbclock, which reported no timing problems.

--ets




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