> On 09/23/2023 3:25 PM CDT Warner Losh via cctalk <cctalk@classiccmp.org>
> wrote:
>
>
> On Sat, Sep 23, 2023, 12:31 PM Paul Koning via cctalk <cctalk@classiccmp.org>
> wrote:
>
> >
> >
> > > On Sep 22, 2023, at 3:07 PM, Chuck Guzis via cctalk <
> > cctalk@classiccmp.org> wrote:
> > >
> > > On 9/22/23 11:34, emanuel stiebler via cctalk wrote:
> > >> There are still some 84pin chips out there(Altera & Xilinx). Sometimes
> > >> they are pulls, or some 5V tolerant xilinx xc95xxxxl
> > >
> > > I still have a few 84 pin PLCC XC95108 5V CPLDs Originally, I did a
> > > tape controller design with one before Xilinx discontinued them. I
> > > figured that using a discontinued part was not the way forward, so I
> > > dropped the project. Xilinx did/does have its ISE design suite, which
> > > is fairly easy to use.
> > > Eventually, it turned out that using a reasonably fast MCU with 5V
> > > tolerant I/O worked just as well and avoided the "mystery in a chip" of
> > > a CPLD.
> > I used an Arduino Feather that way, for my PS-2 to LK201 converter. And
> > while not 5V tolerant, a Raspberry Pico is a particularly powerful and
> > cheap option; one of my projects could run DDCMP at 10 Mb/s including the
> > "integral modem" compatible signaling.
> > As I mentioned, 5V tolerant inputs can, at least for not too high speeds,
> > be done simply by resistive voltage dividers.
>
> What's too fast in absolute terms?
>
> Warner
>
> paul
> >
> >
> >
I can't answer for Paul, but I can tell you how to do approximate calculations
for yourself.
You need to know two things: the equivalent parallel resistance (Thevenin
equivalent) of the two series resistors and the input capacitance of the driven
pin (including stray capacitance.)
If you assume the input+stray capacitance is 10 pF (a reasonable first
approximation) and the resistance is 1000 Ohms, the time constant (time for the
signal to go from 0 to 63% of max) will be 1000 * 10E(-12) seconds or 10,000
picoseconds = 10 nanoseconds. That assumes the 5V output can switch
instantaneously into the 5 mA or so load. I would double that for the real
world. So the signal gets delayed around 20 nS and the output has to drive 5
mA or so.
A more realistic divider might be 5K or 10K resistance for less power
consumption and less strain on the output. With 10K you are looking at a delay
of 100 to 200 nS. If the timing isn't critical you "might" be able to go as
high as 5 MHz that way. But probably more like 1 MHz is more realistic.
I've used voltage divider level translation at about 1 MHz, using something
like 2200 and 4700 ohms for the divider (Thevenin equivalent 1500.)
ymmv
Will
If you want to build a ship, don't drum up people to collect wood and don't
assign them tasks and work, but rather teach them to long for the endless
immensity of the sea.
Antoine de Saint-Exupery
