100% disagree, Verilog and SV are bad tools - very easy to do a bad job with -
penknife grade.
Verilog however is very c like in that it is untyped and prone to all the
consequent tar pits; see above.
VHDL is a good tool which is typed and like the Algol family of languages
precludes many follies.
The 2008 flavor, which is where the tools are curently, is not as pedantic as
the older standards '97 & '83.
However, any non trivial FPGA design work requires an understanding of FPGA
(not SSI/MSI) logic, an HDL and the toolchain(s).
Quite a lot of learning / experience.
Martin
<<<<>>>>
Oh, and Verilog all the way. I just can't with VHDL.
😆
--
Anders Nelson
www.andersknelson.com
<<<<>>>>
Can any of you recommend a good C like tool for programmable logic?
Thank you,
Mike
