On 2023-09-23 12:36 p.m., Paul Koning via cctalk wrote:
On Sep 22, 2023, at 9:30 PM, Martin Bishop <mjd.bis...@emeritus-solutions.com>
wrote:
Paul
I endorse your point regarding Lattice's gouging. Support for anything prior to
the XO parts now costs a significant premium. Their XO2 parts are the most useful
to this community - free tools and 0.5 mm pitch, e.g. 100p & 144p - not dense
but usefully large, 3v3 IO and agricultural assembly.
The Xilinx free tools no longer have license files, which was how Lattice cut
us all off at the pass. The current Vivado ML Standard Edition (tools to
normal people) are free up to the XC7Z030 - which is a fairly serious device.
I have a PDP-11 and space to spare running in the markedly smaller XC7Z010; 16b
/ no MMU, most of the 45 instruction set. FPGA are (organically) memory poor -
perhaps because the access time is ~3 ns. I should think you would be in with
a chance of fitting the 6600 logic, however on a '30 you have 265 x 4 ki by
BRAMs = ~1 Mi By, if more is required either a dedicated external memory device
or DMA to/fr DRAM would be required.
The 6600 model I'm building is a gate level model, so it is cycle-accurate, but
also large. I'm figuring several hundred thousand gates, which makes sense if
you consider the module count for a 6600. A large enough FPGA for that seems
to have enough on-chip memory for both PP and CP memories, leaving only ECS as
off-chip. That's helpful because both PP and CP have tightly constrained
cycles; DRAM would be nearly impossible to make work, though SRAM is doable.
paul
I say get the memory first, who knows what you need will be around
later. I wish you good luck, as FPGA software does what it thinks is
right, not what you think is right.
Ben.
