Paul I endorse your point regarding Lattice's gouging. Support for anything prior to the XO parts now costs a significant premium. Their XO2 parts are the most useful to this community - free tools and 0.5 mm pitch, e.g. 100p & 144p - not dense but usefully large, 3v3 IO and agricultural assembly.
The Xilinx free tools no longer have license files, which was how Lattice cut us all off at the pass. The current Vivado ML Standard Edition (tools to normal people) are free up to the XC7Z030 - which is a fairly serious device. I have a PDP-11 and space to spare running in the markedly smaller XC7Z010; 16b / no MMU, most of the 45 instruction set. FPGA are (organically) memory poor - perhaps because the access time is ~3 ns. I should think you would be in with a chance of fitting the 6600 logic, however on a '30 you have 265 x 4 ki by BRAMs = ~1 Mi By, if more is required either a dedicated external memory device or DMA to/fr DRAM would be required. Martin -----Original Message----- From: Paul Koning [mailto:paulkon...@comcast.net] Sent: 23 September 2023 01:46 To: cctalk@classiccmp.org Cc: Martin Bishop <mjd.bis...@emeritus-solutions.com> Subject: Re: [cctalk] Good C to FPGA/PLA compiler > On Sep 22, 2023, at 3:59 PM, Martin Bishop via cctalk <cctalk@classiccmp.org> > wrote: > > 100% disagree, Verilog and SV are bad tools - very easy to do a bad job with > - penknife grade. > > Verilog however is very c like in that it is untyped and prone to all the > consequent tar pits; see above. > > VHDL is a good tool which is typed and like the Algol family of languages > precludes many follies. > The 2008 flavor, which is where the tools are curently, is not as pedantic as > the older standards '97 & '83. I only know VHDL but I had heard that Verilog is C-like, and yes, C offers an unusually large set of tools to shoot yourself in the foot with. So it wouldn't surprise me that Verilog does likewise, which certainly means that it would be the option to avoid. VHDL is very clearly based on Ada, which like Pascal and ALGOL takes data types seriously rather than only as suggestions the way C does. I've built some very large designs with VHDL, but not because I actually wrote that much code -- a lot is generated code produced from wire lists. But I did write all the models of all the 6000 modules, which does add up. Apart from vendor tools for producing bits for particular FPGAs, you can also find VHDL simulators that just simulate a model but don't deliver it to a particular chip. I use GHDL, which is part of the GCC toolset. Yes, a VHDL compiler, interesting. Among other things, it allows you to link bits in other languages, so I can take device models from the DtCyber emulator and attach them to a VHDL-modeled I/O channel. On FPGAs, it's worth checking what the story is for vendor tools. Some devices and vendors try to suck large sums of money out of you for them; Lattice is an example. Even for small devices (like the ispLSI2032 I used years ago) that expense adds up rapidly. I think they have become somewhat more reasonable now, offering free tools for the smaller devices. I know Xilinx does so, and "smaller" covers a surprising amount of capacity these days. I'm pretty sure a PDP-11 model would fit fine in one of those "free tool" devices, though a CDC 6600 probably won't. paul
