Paul A Zynq '30 has 125,000 Logic Cells, a ZU4EG has 192,000 logic cells. Both can be synthesised with the free tools. You may of course get more LCs on a supported FPGA, vice SoC.
Logic cell is a marketing term, the engineering equivalent would be "LUT4 + FF". Google assures me that a Logic cell is ~15 ASIC gates. So the Z30's fabric looks like it may be a 2 M ASIC gate equivalent device. YMMV I look forward to hearing reports on what its utility is for implementing the 6600. Martin -----Original Message----- From: Paul Koning [mailto:paulkon...@comcast.net] Sent: 23 September 2023 19:36 The 6600 model I'm building is a gate level model, so it is cycle-accurate, but also large. I'm figuring several hundred thousand gates, which makes sense if you consider the module count for a 6600. A large enough FPGA for that seems to have enough on-chip memory for both PP and CP memories, leaving only ECS as off-chip. That's helpful because both PP and CP have tightly constrained cycles; DRAM would be nearly impossible to make work, though SRAM is doable. paul
