On 11/14/2018 03:59 PM, Robin Coxe wrote:
To clarifiy, the B200mini, B200mini-i, and B205mini-i do not have an
on-board GPSDO, but they do have 1 PPS and 10 MHz Reference Inputs.
-Robin
Gahh! Cognitive pollution from other models. I apologize.
So, Chintan, you'll have to set the clock in s
To clarifiy, the B200mini, B200mini-i, and B205mini-i do not have an
on-board GPSDO, but they do have 1 PPS and 10 MHz Reference Inputs.
-Robin
On Wed, Nov 14, 2018 at 12:46 PM Marcus D. Leech via USRP-users <
usrp-users@lists.ettus.com> wrote:
> On 11/14/2018 02:37 PM, Chintan Patel via USRP-u
On 11/14/2018 02:37 PM, Chintan Patel via USRP-users wrote:
Hi,
A conceptual question: for the b205 mini, how does the FPGA get the
64-bit VITA timefield? I know the PPS/10 MHz can be used to sync the
clocks to, but trying to understand how the timestamp is synchronized
to a UTC/known-good re
Hi,
A conceptual question: for the b205 mini, how does the FPGA get the 64-bit
VITA timefield? I know the PPS/10 MHz can be used to sync the clocks to,
but trying to understand how the timestamp is synchronized to a
UTC/known-good reference value. Reading the HDL, it seems that the
timestamp is pr
>>
>> Thank you for your patience.
>>
>>
>> Kind regards,
>>
>> Koen
>>
>>
>>
>> De : Ian Buckley [mailto:i...@ionconcepts.com <mailto:i...@ionconcepts.com>]
>> Envoyé : mercredi 13 juin 2018 20:18
>
u for your patience.
>
>
> Kind regards,
>
> Koen
>
>
>
> De : Ian Buckley [mailto:i...@ionconcepts.com <mailto:i...@ionconcepts.com>]
> Envoyé : mercredi 13 juin 2018 20:18
> À : TIMMEN Koen
> Cc : Michael West; Neel Pandeya; usrp-users@lists.ett
:michael.w...@ettus.com
> <mailto:michael.w...@ettus.com>]
> Envoyé : lundi 11 juin 2018 23:59
> À : TIMMEN Koen
> Cc : Neel Pandeya; Ian Buckley (i...@ionconcepts.com
> <mailto:i...@ionconcepts.com>); usrp-users@lists.ettus.com
> <mailto:usrp-users@lists.ettus.co
: [USRP-users] vita time
Hi Koen,
The way to achieve what you want is to set the device time and then have your
signal generator put timestamps in each packet relative to that time. To tell
your custom block what time to use, you can have a user register that you also
program with the time (or
>
>
>
> *De :* Neel Pandeya [mailto:neel.pand...@ettus.com]
> *Envoyé :* jeudi 7 juin 2018 06:14
> *À :* TIMMEN Koen
> *Cc :* usrp-users@lists.ettus.com
> *Objet :* Re: [USRP-users] vita time
>
>
>
> Hello Koen:
>
>
>
> As Ian requested, could you p
for your responses.
Regards,
Koen Timmen
De : Neel Pandeya [mailto:neel.pand...@ettus.com]
Envoyé : jeudi 7 juin 2018 06:14
À : TIMMEN Koen
Cc : usrp-users@lists.ettus.com
Objet : Re: [USRP-users] vita time
Hello Koen:
As Ian requested, could you please provide additional detail on exactly what
Hello Koen:
As Ian requested, could you please provide additional detail on exactly
what you're trying to do?
Are you merely trying to access the 64-bit FPGA VITA time from within the
RFNoC block?
Which device are you using?
--Neel Pandeya
On 5 June 2018 at 09:24, Ian Buckley via USRP-user
Koen,
Can you expand a little on the functionality you need pls, its not fully clear
enough to me to make a suggestion.
Are you trying to extract time from incoming samples or apply time to samples
you are processing?
-Ian
> On Jun 5, 2018, at 7:36 AM, TIMMEN Koen via USRP-users
> wrote:
>
Hello all,
Currently I'm working on a RFNoC block that requires a known time reference,
but I have trouble making this value available. Ideally I would like to have
the value available in a register designated to the block.
As I understand, a time reference is available through the CHDR, but..
Hey Dmitry,
for the DDC case, we always use the timestamp for the first package. If
your decim is 2, then every other timestamp is effectively discarded.
The counter your referring to is thus more relevant for the DUC use case.
Cheers,
Martin
On 01/16/2018 01:51 AM, Дмитрий Михайличенко via USRP
2018-01-16 3:31 GMT+03:00 Martin Braun via USRP-users <
usrp-users@lists.ettus.com>:
> On 01/11/2018 01:38 AM, Дмитрий Михайличенко via USRP-users wrote:
> > Hi,
> >
> > I am trying to understand timestamp tracking in FPGA and noticed one
> > possible issue in axi_rate_change.v module .
> >
> > VI
On 01/11/2018 01:38 AM, Дмитрий Михайличенко via USRP-users wrote:
> Hi,
>
> I am trying to understand timestamp tracking in FPGA and noticed one
> possible issue in axi_rate_change.v module .
>
> VITA time in packet headers is counted in ticks of master clock
> frequency, i.e. 200 MHz. For me it
Hi,
I am trying to understand timestamp tracking in FPGA and noticed one
possible issue in axi_rate_change.v module .
VITA time in packet headers is counted in ticks of master clock frequency,
i.e. 200 MHz. For me it looks like axi_rate_change adjusts time by adding
time from the first packet in
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