2018-01-16 3:31 GMT+03:00 Martin Braun via USRP-users < usrp-users@lists.ettus.com>:
> On 01/11/2018 01:38 AM, Дмитрий Михайличенко via USRP-users wrote: > > Hi, > > > > I am trying to understand timestamp tracking in FPGA and noticed one > > possible issue in axi_rate_change.v module . > > > > VITA time in packet headers is counted in ticks of master clock > > frequency, i.e. 200 MHz. For me it looks like axi_rate_change adjusts > > time by adding time from the first packet in a group to number of > > samples sent out which are actually downsampled in case of DDC and may > > have lower sampling frequency. That is probably incorrect unless I > > understand the code. Does it only work because output packet always > > starts from input packet boundary so vita_time_reg is never used? > > Dmitry, > > a couple of notes: axi_rate_change is used in modules such as the > DDC/DUC blocks which don't actually run at the sample clock rate. So the > only reference for time is the sample count, not a clock count. > And yes, input/output packet boundaries are also matched. For > interpolation by factor M, you will input 1 packet and get M packets of > identical size. > Also, the master clock rate (which is the 200 MHz clock in this case) is > used as a timing reference. > > Not sure if this answers your questions. Let us know if it doesn't! > > -- M > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com Hi Martin, thank you for reply. I understand that the time reference is the sample count. Let me clarify my question. Assume we have ADC running at 200 MHz and user app requests 20 MHz receive sampling rate. It means that DDC block will perform downconversion by 10 times. So for 10 input samples one output sample is produced by DDC. And in that case axi_rate_change block at line https://github.com/ EttusResearch/fpga/blob/maint/usrp3/lib/rfnoc/axi_rate_change.v#L458 adds counter of 200 MHz samples (time from the header) to counter of 20 MHz samples (produced by DDC). Is this correct? thanks, Dmitry
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