Hi, I am trying to understand timestamp tracking in FPGA and noticed one possible issue in axi_rate_change.v module .
VITA time in packet headers is counted in ticks of master clock frequency, i.e. 200 MHz. For me it looks like axi_rate_change adjusts time by adding time from the first packet in a group to number of samples sent out which are actually downsampled in case of DDC and may have lower sampling frequency. That is probably incorrect unless I understand the code. Does it only work because output packet always starts from input packet boundary so vita_time_reg is never used? thanks, Dmitry
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