Hello again, Thank you for answering my question. I do still have a few questions though.
What do the timestamps in each packet serve for exactly? Are you talking about the CHDR packets here? I saw that in the CHDR format ‘fractional time’ was optional, but did not understand how to activate this option. I assumed it would be handled internally in the AXI wrapper and NoC shell. But as I understand now, one has to write his own code that adds this part of the payload? My original plan was based on what you suggest as well, to make the time available in a register and upon reaching some future start time, my block will transmit the corresponding sample. However, this does not answer the question of where to find the value to store inside the register and update it as time actually progresses. Is it as simple as coding a counter and counting the number of passed clock cycles? Sorry if I seem to ask for the obvious, it’s all still relatively new to me. Kind regards, Koen De : Michael West [mailto:michael.w...@ettus.com] Envoyé : lundi 11 juin 2018 23:59 À : TIMMEN Koen Cc : Neel Pandeya; Ian Buckley (i...@ionconcepts.com); usrp-users@lists.ettus.com Objet : Re: [USRP-users] vita time Hi Koen, The way to achieve what you want is to set the device time and then have your signal generator put timestamps in each packet relative to that time. To tell your custom block what time to use, you can have a user register that you also program with the time (or some future start time). Regards, Michael On Wed, Jun 6, 2018 at 11:24 PM, TIMMEN Koen via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hello, My block is a signal generator and each sample needs to be transmitted at an accurately known instant. The samples themselves do not need to hold this information. The device I am using is the X310. What Neel Pandeya is suggesting sounds like exactly what I’m trying to do. Thank you for your responses. Regards, Koen Timmen De : Neel Pandeya [mailto:neel.pand...@ettus.com<mailto:to%3aneel.pand...@ettus.com>] Envoyé : jeudi 7 juin 2018 06:14 À : TIMMEN Koen Cc : usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> Objet : Re: [USRP-users] vita time Hello Koen: As Ian requested, could you please provide additional detail on exactly what you're trying to do? Are you merely trying to access the 64-bit FPGA VITA time from within the RFNoC block? Which device are you using? --Neel Pandeya On 5 June 2018 at 09:24, Ian Buckley via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Koen, Can you expand a little on the functionality you need pls, its not fully clear enough to me to make a suggestion. Are you trying to extract time from incoming samples or apply time to samples you are processing? -Ian On Jun 5, 2018, at 7:36 AM, TIMMEN Koen via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hello all, Currently I’m working on a RFNoC block that requires a known time reference, but I have trouble making this value available. Ideally I would like to have the value available in a register designated to the block. As I understand, a time reference is available through the CHDR, but.. not all the time? It is optional I read in the manual. Is this a toggle that can be set by the user? Or is there another way that I am able to obtain the device time reference available in a user register? Kind regards, Koen _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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