Signed-off-by: Shengzhou Liu
---
include/configs/ls2080ardb.h | 39 ---
1 file changed, 32 insertions(+), 7 deletions(-)
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 48c3a5397f..650db2f594 100644
--- a/include/configs
Signed-off-by: Shengzhou Liu
---
include/configs/ls1021atwr.h | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 0f20e5e2cc..5be61ad7b6 100644
--- a/include/configs/ls1021atwr.h
+++ b/include
Signed-off-by: Shengzhou Liu
---
include/configs/ls1043a_common.h | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index a24d0062d2..140ea23902 100644
--- a/include/configs/ls1043a_common.h
Signed-off-by: Shengzhou Liu
---
include/configs/ls1046a_common.h | 11 +++
include/configs/ls1046ardb.h | 6 ++
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 6d501b9c54..e7b1425c15
> -Original Message-
> From: Mingkai Hu
> Sent: Wednesday, November 01, 2017 7:14 PM
> To: York Sun
> Cc: Shengzhou Liu ; u-boot@lists.denx.de
> Subject: RE: [U-Boot] [PATCH 1/4] arm64: ls1043ardb: Add sd_bootcmd for
> distro fallback in case of sdboot
>
>
&
Signed-off-by: Shengzhou Liu
---
include/configs/ls1021atwr.h | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 0e5b004868..45fb94a889 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs
Signed-off-by: Shengzhou Liu
---
include/configs/ls1046a_common.h | 8 +++-
include/configs/ls1046ardb.h | 6 ++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index e5159d8f1a..953f3ae70e 100644
Signed-off-by: Shengzhou Liu
---
include/configs/ls2080ardb.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index b309d79586..9458fda173 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs
Signed-off-by: Shengzhou Liu
---
include/configs/ls1043a_common.h | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index f064d5c24a..976c031574 100644
--- a/include/configs/ls1043a_common.h
+++ b
or USB disk, if it fails to detect external
storage disk, fall back to nor/qspi boot.
Signed-off-by: Shengzhou Liu
---
v3: updated to load_addr for installer
v4: fix a typo in initrd_high
configs/ls1043ardb_defconfig| 1 +
configs/ls1043ardb_sdcard_defconfig | 1 +
include/configs
or USB disk, if it fails to detect external
storage disk, fall back to nor/qspi boot.
Signed-off-by: Shengzhou Liu
---
v3: updated to load_addr for installer
configs/ls1043ardb_defconfig| 1 +
configs/ls1043ardb_sdcard_defconfig | 1 +
include/configs/ls1043a_common.h| 67
or USB disk, if it fails to detect external
storage disk, fall back to nor/qspi boot.
Signed-off-by: Shengzhou Liu
---
v2: add nor/qspi boot
configs/ls1043ardb_defconfig| 1 +
configs/ls1043ardb_sdcard_defconfig | 1 +
include/configs/ls1043a_common.h| 67
or USB disk.
Signed-off-by: Shengzhou Liu
---
configs/ls1043ardb_defconfig| 1 +
configs/ls1043ardb_sdcard_defconfig | 1 +
include/configs/ls1043a_common.h| 52 +++--
3 files changed, 41 insertions(+), 13 deletions(-)
diff --git a/configs
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Tuesday, April 11, 2017 1:14 AM
> To: Shengzhou Liu ; u-boot@lists.denx.de
> Subject: Re: [PATCH] board/t1024rdb: enable board-level reset when issuing
> reset command
>
> On 04/10/2017 01:14
As board-specific reset logic, it needs to issue reset signal
via CPLD when issuing 'reset' command in u-boot, this patch
solves the issue of reset command not working on T1024RDB.
Signed-off-by: Shengzhou Liu
---
board/freescale/t102xrdb/t102xrdb.c | 7 +++
1 file changed, 7
Signed-off-by: Shengzhou Liu
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a99b1c6..25588c8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
As board-specific reset logic, it needs to issue reset signal
via CPLD when issuing 'reset' command in u-boot, this patch
solves the issue of reset command not working on T1024RDB.
Signed-off-by: Shengzhou Liu
---
v2: add build condition.
board/freescale/t102xrdb/t102xrdb.c | 7 +
As board-specific reset logic, it needs to issue reset signal
via CPLD when issuing 'reset' command in u-boot, this patch
solves the issue of reset command not working on T1024RDB.
Signed-off-by: Shengzhou Liu
---
board/freescale/t102xrdb/t102xrdb.c | 5 +
1 file changed, 5
fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu
---
v2: fix warning on e5500 platform.
v3: rebased.
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 +-
arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 +-
arch/powerpc
Fix following warning in case multiple erratum macro was not defined.
warning: unused variable 'tmp'
warning: unused variable 'ddr_freq'
Signed-off-by: Shengzhou Liu
---
v2: fix compile issue on some platforms.
drivers/ddr/fsl/fsl_ddr_gen4.c | 57 ++---
fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu
---
v2: fix warning.
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 +-
arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 +-
arch/powerpc/include/asm/config_mpc85xx.h
Enable ERRATUM_A009942 workaround for B-series and T-series platforms.
Signed-off-by: Shengzhou Liu
---
arch/powerpc/include/asm/config_mpc85xx.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index
Optimize board-specific cpo for erratum A-009942 on b4860qds,
ls1043aqds, ls1043ardb, ls1046aqds, ls1046ardb, ls2080ardb,
t102xqds, t102xrdb, t1040qds, t104xrdb, t208xqds, t208xrdb,
t4qds, t4rdb boards.
Signed-off-by: Shengzhou Liu
---
board/freescale/b4860qds/ddr.c | 3 +++
board/freescale
fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 +-
arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 +-
arch/powerpc/include/asm/config_mpc85xx.h | 2 -
board
Fix following warning in case multiple erratum macro was not defined.
warning: unused variable 'tmp'
warning: unused variable 'ddr_freq'
Signed-off-by: Shengzhou Liu
---
drivers/ddr/fsl/fsl_ddr_gen4.c | 43 +-
1 file changed,
Update CONFIG_LS2080A to CONFIG_FSL_LSCH3 to make those workaround
implementing of erratum reusable for more SoCs.
Signed-off-by: Shengzhou Liu
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl
> -Original Message-
> From: york sun
> Sent: Wednesday, November 09, 2016 1:04 AM
> To: Shengzhou Liu ; u-boot@lists.denx.de
> Subject: Re: [PATCH 1/3] fsl/ddr: Revise erratum a009942 and clean related
> erratum
>
> On 11/08/2016 02:39 AM, Shengzhou Liu wrote
> -Original Message-
> From: york sun
> Sent: Tuesday, November 08, 2016 1:04 AM
> To: Shengzhou Liu ; u-boot@lists.denx.de
> Subject: Re: [PATCH 1/3] fsl/ddr: Revise erratum a009942 and clean related
> erratum
> >
> > York,
> >
> > This change(
fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu
---
v2: fix a typo
v3: add reading POR value of debug_29 before changing.
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 +-
arch/powerpc/cpu/mpc85xx/cpu_init.c
fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu
---
v2: fix a typo
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 +-
arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 +-
arch/powerpc/include/asm/config_mpc85xx.h | 2
> -Original Message-
> From: york sun
> Sent: Friday, November 04, 2016 11:20 PM
> To: Shengzhou Liu ; u-boot@lists.denx.de
> Subject: Re: [PATCH 1/3] fsl/ddr: Revise erratum a009942 and clean related
> erratum
>
> On 11/04/2016 04:18 AM, Shengzhou Liu wro
fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 +-
arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 +-
arch/powerpc/include/asm/config_mpc85xx.h | 2 -
board
Fix following warning in case multiple erratum macro was not defined.
warning: unused variable 'tmp'
warning: unused variable 'ddr_freq'
Signed-off-by: Shengzhou Liu
---
drivers/ddr/fsl/fsl_ddr_gen4.c | 43 +-
1 file changed,
Enable ERRATUM_A009942 workaround for B-series and T-series platforms.
Signed-off-by: Shengzhou Liu
---
arch/powerpc/include/asm/config_mpc85xx.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index
> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of york sun
> Sent: Thursday, October 27, 2016 3:57 AM
> To: Hamish Martin ; u-
> b...@lists.denx.de
> Subject: Re: [U-Boot] [PATCH] powerpc/t2080: DDR controller erratum A-009942
> I got a notice from our h
fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 ++-
arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 +-
arch/powerpc/include/asm/config_mpc85xx.h | 2 -
board
Enable ERRATUM_A009942 workaround for B-series and T-series platforms.
Signed-off-by: Shengzhou Liu
---
arch/powerpc/include/asm/config_mpc85xx.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index
Signed-off-by: Shengzhou Liu
---
arch/arm/include/asm/arch-ls102xa/config.h | 1 +
board/freescale/ls1021atwr/ls1021atwr.c| 7 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
b/arch/arm/include/asm/arch-ls102xa/config.h
index
> -Original Message-
> From: Gong Qianyu [mailto:qianyu.g...@nxp.com]
> Sent: Friday, August 26, 2016 7:29 PM
> To: u-boot@lists.denx.de; york sun
> Cc: Prabhakar Kushwaha ; Mingkai Hu
> ; Shaohui Xie ; Zhiqiang
> Hou ; Wenbin Song ;
> Shengzhou Liu ; Qianyu Gong
> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Gong
> Qianyu
> Sent: Friday, August 26, 2016 7:28 PM
> To: u-boot@lists.denx.de; york sun
> Cc: Zhiqiang Hou ; Wenbin Song
> ; Mingkai Hu
> Subject: [U-Boot] [PATCH 1/8] drivers/ddr/fsl: add DEBUG_38
From: York Sun
DDR controller 5.2.1 has this erratum A008511 partially fixed.
The workaround needs to be adjusted to take advantage of Vref
training. This patch enables the training and force output
enable to be off.
Erratum A009803 requires the controller to be idel before enabling
address pari
From: York Sun
32 more debug registers are added for newer DDR controllers.
Signed-off-by: York Sun
Signed-off-by: Shengzhou Liu
---
drivers/ddr/fsl/fsl_ddr_gen4.c | 2 +-
drivers/ddr/fsl/interactive.c | 4 ++--
include/fsl_ddr_sdram.h| 2 +-
include/fsl_immap.h| 3
) are implimented in future.
Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/LS1012AFRDM.
Signed-off-by: Shengzhou Liu
---
Makefile | 1 +
arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 +-
board/freescale/ls1012afrdm/ls1012afrdm.c
DDR erratum A008336 only applies to DDR controller v5.2.0.
DDR controller v5.2.1 already has default 0x43b30002 in
EDDRTQCR1 register for optimal performance.
Signed-off-by: Shengzhou Liu
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions
> -Original Message-
> From: york sun
> Sent: Friday, August 12, 2016 3:45 AM
> To: Shengzhou Liu ; u-boot@lists.denx.de
> Subject: Re: [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver
>
> > +#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
> > +#def
combine the two to one patch?
Shengzhou
From: york sun
Sent: Friday, August 12, 2016 1:56 PM
To: Shengzhou Liu ; u-boot@lists.denx.de
Subject: RE: [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver
I am not suggesting remove the macros. Please try to compile after applying
first patch. You
Let's use common MMDC driver for DDR initialization on
LS1012ARDB, LS1012AQDS, LS1012AFRDM boards.
Signed-off-by: Shengzhou Liu
---
v2: no change
board/freescale/ls1012afrdm/ls1012afrdm.c | 116 --
board/freescale/ls1012aqds/ls1012aqds.c
in future.
Signed-off-by: Shengzhou Liu
---
v2: add a compiling condition to check if CONFIG_MMDC_* is defined.
Makefile | 1 +
arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 +-
drivers/ddr/fsl/Makefile | 1
in future.
Signed-off-by: Shengzhou Liu
---
Makefile | 1 +
arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 +
drivers/ddr/fsl/Makefile | 1 +
drivers/ddr/fsl/fsl_mmdc.c| 152
Let's use common MMDC driver for DDR initialization on
LS1012ARDB, LS1012AQDS, LS1012AFRDM boards.
Signed-off-by: Shengzhou Liu
---
board/freescale/ls1012afrdm/ls1012afrdm.c | 116 --
board/freescale/ls1012aqds/ls1012aqds.c
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Wednesday, June 01, 2016 12:04 AM
> To: Shengzhou Liu ; u-boot@lists.denx.de
> Shengzhou,
>
> If you have to use an odd number for clk_adj, we can go ahead to merge
> these patches. In my exp
We should use unified setup_ddr_tlbs() for spl boot and non-spl boot
to make sure 'M' bit is set for DDR TLB to maintain cache coherence.
Signed-off-by: Shengzhou Liu
---
board/freescale/b4860qds/ddr.c | 8 +++-
board/freescale/t102xqds/ddr.c | 5 ++---
board/freescale/t102xrdb
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Tuesday, May 17, 2016 12:55 AM
> To: Shengzhou Liu ; u-boot@lists.denx.de
> Subject: Re: [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl
>
> Shengzhou,
>
> Your unders
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Thursday, May 19, 2016 4:28 AM
> To: Shengzhou Liu ; u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH v2] armv8/ls2080ardb: Update DDR timing to
> support more UDIMMs
> >
>
> Shengz
Add condition of checking the enabled of address parity
for erratum A-009803, if parity is not enabled, the
workaround of erratum A-009803 should not be applied.
Signed-off-by: Shengzhou Liu
---
drivers/ddr/fsl/fsl_ddr_gen4.c | 42 +++---
1 file changed, 23
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Monday, May 23, 2016 11:33 PM
> To: Shengzhou Liu ; u-boot@lists.denx.de
> Subject: Re: [PATCH] driver/ddr/fsl: Force enabling parity for A-009803
> Shengzhou,
>
> My point is you should fo
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Friday, May 20, 2016 11:29 PM
> To: Shengzhou Liu ; u-boot@lists.denx.de
> Subject: Re: [PATCH] driver/ddr/fsl: Force enabling parity for A-009803
> >
>
> Shengzhou,
>
> It looks b
Default address parity is disabled for DDR4 UDIMM for considing
performance, it needs to enable parity for A-009803 workaround.
Signed-off-by: Shengzhou Liu
---
drivers/ddr/fsl/options.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
During DDR-2133 operation, the transmit data eye margins determined
during the memory controller initialization may be sub-optimal, set
DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set.
Signed-off-by: Shengzhou Liu
---
v2: rebase
arch/arm/include/asm/arch-fsl-layerscape/con
During DDR-2133 operation, the transmit data eye margins determined
during the memory controller initialization may be sub-optimal, set
DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set.
Signed-off-by: Shengzhou Liu
---
arch/arm/include/asm/arch-fsl-layerscape/config.h
The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series,
but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs.
We should update it to adapt the case that clk_adjust is odd data.
Signed-off-by: Shengzhou Liu
---
drivers/ddr/fsl/ctrl_regs.c | 11 +--
1 file
This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.
Signed-off-by: Shengzhou Liu
---
board/freescale/ls1021aqds/ddr.h | 28 ++--
board/freescale/ls1043aqds/ddr.h | 28
> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of
> ying.zh...@freescale.com
> Sent: Friday, April 15, 2016 2:19 PM
> To: u-boot@lists.denx.de
> Cc: york...@freescale.com; Ying Zhang
> Subject: [U-Boot] [PATCH 2/2] board/t4240rdb: some ethernet ports
>
> -Original Message-
> From: Shengzhou Liu
> Sent: Friday, April 15, 2016 3:45 PM
> To: 'ying.zh...@freescale.com' ; u-
> b...@lists.denx.de
> Cc: york...@freescale.com; Ying Zhang
> Subject: RE: [U-Boot] [PATCH 2/2] board/t4240rdb: some etherne
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.
Signed-off-by: Shengzhou Liu
---
v2: moved part 2 of 2 to public soc.c
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 36
: TS1GLH72V1H
Signed-off-by: Shengzhou Liu
---
v2: verified lower rate, for 1333MT/s no changes are necessary.
board/freescale/ls2080ardb/ddr.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h
index bda9d4a
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Wednesday, April 06, 2016 11:26 PM
> To: Shengzhou Liu ; u-boot@lists.denx.de
> Subject: Re: [PATCH] mmc:fsl_esdhc: fix invalidate dcache scope
> >
>
> Shenghzou,
>
> This is not a c
commit 4683b220655 "mmc:fsl_esdhc invalidate dcache before read"
intended for ARM, which broke on PowerPC(caused memory allocation
failure under SD boot), so add condition CONFIG_ARM.
Signed-off-by: Shengzhou Liu
---
drivers/mmc/fsl_esdhc.c | 2 ++
1 file changed, 2 insertions(+)
di
-by: Shengzhou Liu
---
board/freescale/ls2080ardb/ddr.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h
index bda9d4a..7274778 100644
--- a/board/freescale/ls2080ardb/ddr.h
+++ b/board/freescale/ls2080ardb
The initial training for the DDRC may provide results that are not
optimized. The workaround provides better read timing margins.
Signed-off-by: Shengzhou Liu
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
drivers/ddr/fsl/fsl_ddr_gen4.c| 7 +++
include
Per the latest erratum document, update step 4 and step 8, only
DEBUG_29[21] is changed, all other bits should not be changed.
Signed-off-by: Shengzhou Liu
---
drivers/ddr/fsl/fsl_ddr_gen4.c | 10 +++---
include/fsl_ddr_sdram.h| 3 +++
2 files changed, 10 insertions(+), 3 deletions
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.
Signed-off-by: Shengzhou Liu
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 18 ++
arch/arm/include/asm
Add support of address parity for DDR4 UDIMM or discrete memory.
It requires to configurate corresponding MR5[2:0] and TIMING_CFG_7[PAR_LAT].
Parity can be turned on/off by hwconfig, e.g. hwconfig=fsl_ddr:parity=on.
Signed-off-by: Shengzhou Liu
---
v2: Integrated York's comments.
During initial DDR training, false parity errors may be detected.
This patch adds workaround to fix the erratum.
Tested on LS2085QDS and LS2080RDB.
Signed-off-by: Shengzhou Liu
---
v2: Integrated York's comments.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
drivers/dd
Add support of command/address parity for DDR4 UDIMM or discrete memory.
It requires to configurate corresponding MR5[2:0] and TIMING_CFG_7[PAR_LAT].
Parity can be turned on/off by hwconfig, e.g. hwconfig=fsl_ddr:parity=on.
Signed-off-by: Shengzhou Liu
---
doc/README.fsl-ddr | 8
erratum.
Signed-off-by: Shengzhou Liu
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
drivers/ddr/fsl/fsl_ddr_gen4.c| 44 ---
2 files changed, 40 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b
DDR erratum A-009942 is also applicable to LS1043A.
Signed-off-by: Shengzhou Liu
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index
Remove duplicated SDRAM_INTERVAL_BSTOPRE from mpc83xx.h,
which has been defined in fsl_ddr_sdram.h
Signed-off-by: Shengzhou Liu
---
include/mpc83xx.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index a6d721a..b5a0bbf 100644
--- a/include/mpc83xx.h
During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.
Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.
Signed-off-by: Shengzhou Liu
---
arch/arm
During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.
Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.
Signed-off-by: Shengzhou Liu
---
arch/arm
workaround is not needed.
Signed-off-by: Shengzhou Liu
---
v2: add more comments.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++
arch/arm/include/asm/arch-ls102xa/config.h| 1 +
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++
arch/powerpc/include/asm
Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired value after DDR initialization has completed.
Signed-off-by: Shengzhou Liu
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 3
Signed-off-by: Shengzhou Liu
---
arch/arm/cpu/armv7/ls102xa/cpu.c | 8
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 5 +
2 files changed, 13 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 14ae2a3..74cd2cb
move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h
to make it public for both ARM and POWER SoCs.
Signed-off-by: Shengzhou Liu
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 2 +-
arch/powerpc/cpu/mpc85xx/cpu_init.c| 2 +-
arch/powerpc/cpu/mpc85xx
DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.
Signed-off-by: Shengzhou Liu
---
arch/powerpc/include/asm/config_mpc85xx.h | 2 ++
drivers/ddr/fsl/fsl_ddr_gen4.c| 9 ++---
include
DDR Errata A008378 only exists on LS102x Rev1, it has been
fixed on LS102x Rev2.
Signed-off-by: Shengzhou Liu
---
drivers/ddr/fsl/arm_ddr_gen3.c | 11 +++
drivers/ddr/fsl/fsl_ddr_gen4.c | 9 ++---
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/fsl
Add get_svr_ver_major() and get_svr_ver_minor() helper.
Signed-off-by: Shengzhou Liu
---
arch/arm/cpu/armv7/ls102xa/cpu.c | 14 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +++
2 files changed, 17 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa
T2081 rev 1.1 changes MEM_PLL_RAT in RCW which requires new parsing for ratio.
Signed-off-by: Shengzhou Liu
---
arch/powerpc/cpu/mpc85xx/speed.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index
Per new requirement, change default core frequency
from previous 1400MHz to 1200MHz to save power.
Signed-off-by: Shengzhou Liu
---
board/freescale/t102xrdb/t1023_rcw.cfg | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/t102xrdb/t1023_rcw.cfg
b/board
eMMC has no CD and WP pins, it needs to add board-specific
board_mmc_getcd() and board_mmc_getwp() in SPL to support
eMMC boot without external SD card inserted.
Signed-off-by: Shengzhou Liu
---
board/freescale/t102xrdb/spl.c | 24
1 file changed, 24 insertions(+)
diff
Update t4160/t4080 serdes according to latest reference manual rev2.
Signed-off-by: Shengzhou Liu
---
arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
b/arch/powerpc
Add support for NOR flash and GPIO/I2C switch control on RevC.
- NOR support
- bank0/bank4 switch
- SD/eMMC switch
- board version
Signed-off-by: Shengzhou Liu
---
v2: updated rcw.
board/freescale/t102xrdb/README| 18 +++--
board/freescale/t102xrdb/t1023_rcw.cfg | 2 +-
board
Add support for NOR flash and GPIO/I2C switch control on RevC.
- NOR support
- bank0/bank4 switch
- SD/eMMC switch
- board version
Signed-off-by: Shengzhou Liu
---
board/freescale/t102xrdb/README | 18 +++--
board/freescale/t102xrdb/t102xrdb.c | 141
Initialize LCR rigister to configure
green LED for Link, yellow LED for Active.
Signed-off-by: Shengzhou Liu
---
drivers/net/phy/realtek.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 79452a8..bba48da 100644
--- a
e-tree/soc@ffe00/fman@40/port@88000/
Signed-off-by: Shengzhou Liu
---
arch/powerpc/cpu/mpc85xx/t1024_ids.c | 3 +--
arch/powerpc/include/asm/fsl_liodn.h | 6 ++
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c
b/arch/powerpc/cpu/mpc85xx/t
RTL8211F needs to enalbe TXDLY for RGMII during
phy initialization, so move it to rtl8211f_config
for early initialization.
Signed-off-by: Shengzhou Liu
cc: Joe Hershberger
---
v2: add default page and use macro instead of magic number.
drivers/net/phy/realtek.c | 33
T2080RDB RevC uses new SODIMM 1867MT/s instead of previous 1600MT/s.
So update RCW to support new DDR frequency 1867MT/s by default.
Reserve the old 1600MT/s in comment for users in needed.
Signed-off-by: Shengzhou Liu
---
board/freescale/t208xrdb/t2080_rcw.cfg | 5 -
1 file changed, 4
CS4315 PHY doesn't support phy-reset by software, it
needs to reset it by hardware via CPLD control.
Signed-off-by: Shengzhou Liu
---
board/freescale/t208xrdb/cpld.h | 3 +++
board/freescale/t208xrdb/t208xrdb.c | 7 +++
2 files changed, 10 insertions(+)
diff --git a/board/free
CS4315 PHY doesn't phy reset by software, it needs to
reset it by hardware reset via CPLD control.
Signed-off-by: Shengzhou Liu
---
board/freescale/t208xrdb/cpld.h | 3 +++
board/freescale/t208xrdb/t208xrdb.c | 7 +++
2 files changed, 10 insertions(+)
diff --git a/board/free
Use fdt_setprop_string instead of fdt_setprop to fix string length.
Signed-off-by: Shengzhou Liu
---
board/freescale/t102xqds/eth_t102xqds.c | 9 +
board/freescale/t102xrdb/eth_t102xrdb.c | 4 ++--
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/board/freescale/t102xqds
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