DDR Errata A008378 only exists on LS102x Rev1, it has been
fixed on LS102x Rev2.
Signed-off-by: Shengzhou Liu <shengzhou....@freescale.com>
---
drivers/ddr/fsl/arm_ddr_gen3.c | 11 +++++++++++
drivers/ddr/fsl/fsl_ddr_gen4.c | 9 ++++++---
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index c139da6..e059b83 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -152,6 +152,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t
*regs,
}
}
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008378
+#include <asm/arch-ls102xa/immap_ls102xa.h>
+#define IS_ACC_ECC_EN(v) ((v) & 0x4)
+#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
+ if (get_svr_ver_major() < 2) {
+ if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
+ IS_DBI(regs->ddr_sdram_cfg_3))
+ ddr_setbits32(ddr->debug[28], 0x9 << 20);
+ }
+#endif
+
/*
* For RDIMMs, JEDEC spec requires clocks to be stable before reset is
* deasserted. Clocks start when any chip select is enabled and clock
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 4eef047..0b0bcd2 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -172,12 +172,15 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t
*regs,
}
}
#ifdef CONFIG_SYS_FSL_ERRATUM_A008378
+#include <asm/arch-ls102xa/immap_ls102xa.h>
/* Erratum applies when accumulated ECC is used, or DBI is enabled */
#define IS_ACC_ECC_EN(v) ((v) & 0x4)
#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
- if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
- IS_DBI(regs->ddr_sdram_cfg_3))
- ddr_setbits32(ddr->debug[28], 0x9 << 20);
+ if (get_svr_ver_major() < 2) {
+ if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
+ IS_DBI(regs->ddr_sdram_cfg_3))
+ ddr_setbits32(ddr->debug[28], 0x9 << 20);
+ }
#endif
/*
--
2.1.0.27.g96db324
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