From: Leon Schuermann
This commit fixes PMP address access checks with non page-aligned PMP
regions on harts with MPU enabled. Without this change, the presence
of an MPU in the virtual CPU model would influence the PMP address
check behavior when an access size was unknown (`size == 0
From: Leon Schuermann
When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP
configuration lock bits must not apply. While this behavior is
implemented for the pmpcfgX CSRs, this bit is not respected for
changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
writes
Public bug reported:
This is a rewrite for https://bugs.launchpad.net/qemu/+bug/1670377
QEMU 2.6 or later
tigervncviwer 1.6
Once get into grub boot interface(choose boot os, or recovery mode),
keep pressing arrow down button for couple times, qemu will close the
connection, vnc used zrle mode.
** Description changed:
This is a rewrite for https://bugs.launchpad.net/qemu/+bug/1670377
QEMU 2.6 or later
- tigervncviwer 1.6
+ tigervncviwer 1.6
Once get into grub boot interface(choose boot os, or recovery mode),
- keep pressing arrow down button for couple times, qemu will clos
/0x5579e7b6d730: shared -> disconnected
** Changed in: qemu
Assignee: (unassigned) => leon (liayan)
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1686390
Title:
vnc server closed socke
using bit[11-12] of opcode as acc is not correct for ASE_MIPS16 instructions.
doing so generates RI/DSPDIS exception when decoding MIPS16 MULT/DIV.
Signed-off-by: Leon Yu
---
target-mips/translate.c | 14 +++---
1 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target
to a bios
device with a nop write callback.
Signed-off-by: James Hogan
Cc: Paul Burton
Cc: Leon Alrae
Cc: Aurelien Jarno
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 14 --
1 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mi
s fixed by making the bios copy ram writeable, but loaded via
rom_add_blob_fixed() so that it it restored on reset. That's not as
volatile as real hardware but should be good enough.
Signed-off-by: James Hogan
Cc: Paul Burton
Cc: Leon Alrae
Cc: Aurelien Jarno
Cc: Andreas Färber
Signed-off
& MIPS_HFLAG_BDS16) &&
> + !(ctx.hflags & MIPS_HFLAG_BDS32)) {
IMHO it would look nicer if you made this condition shorter by ORing BDS
hflags.
Feel free to add:
Reviewed-by: Leon Alrae
Regards,
Leon
ping - would anyone help me and review the remaining patches in this series?
On 22/08/2014 12:26, Leon Alrae wrote:
> ping
>
> Anybody? There hasn't been any feedback on this patchset for almost 2
> months now...
>
> On 12/08/2014 12:36, Leon Alrae wrote:
>> ping
&g
Hi James,
On 26/09/2014 13:03, James Hogan wrote:
> Hi Leon,
>
> On 27/06/14 16:21, Leon Alrae wrote:
>> /* MIPS64 MIPS-3D ASE support. */
>> #define I16 INSN_MIPS16
>> @@ -1209,6 +1215,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
>> them f
Hi James,
On 26/09/2014 13:44, James Hogan wrote:
> Hi Leon,
>
> On 27/06/14 16:21, Leon Alrae wrote:
>> @@ -1215,6 +1217,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
>> them first. The assemblers uses a hash table based on the
>> instruction n
maintainer assisting Aurelien?
Leon
Hi Peter,
On 01/10/2014 17:32, Peter Maydell wrote:
> On 1 October 2014 16:35, Leon Alrae wrote:
>> I noticed that it's quite difficult to get target-mips changes
>> reviewed/accepted. There is already a queue of relatively big features
>> and bug fixes which are stu
Hi Yongbok,
On 02/10/2014 17:10, Yongbok Kim wrote:
> Hi,
>
> Overall looking good but has issues with not freeing tcg_temps and some
> style problem which
> failed with the checkpatch.pl script.
I remember that checkpatch.pl just hung on this patch, probably due to
macros.
Regards,
Leon
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v2:
* move new CPU definition to a separate patch
---
target-mips/mips-defs.h | 28 +++-
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index
elien. More detailed
changelog included in the separate patches.
* added missing zero register case for LSA, ALIGN and BITSWAP instructions
Leon Alrae (17):
target-mips: define ISA_MIPS64R6
target-mips: signal RI Exception on instructions removed in R6
target-mips: add SELEQZ and SELNEZ instructions
Move DSP and Loongson instruction to *_legacy functions as they have been
removed in R6.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/translate.c | 195
1 file changed, 98 insertions(+), 97 deletions(-)
diff --git a
The encoding of PREF, CACHE, LLD and SCD instruction changed in MIPS32R6.
Additionally, the hint codes in PREF instruction greater than or
equal to 24 generate Reserved Instruction Exception.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
disas/mips.c| 4
target
The encoding of LL and SC instruction has changed in MIPS32 Release 6.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
Reviewed-by: James Hogan
---
v4:
* fix disas mask for ll and sc
* remove unnecessary check_insn_opc_removed line
---
disas/mips.c| 9 -
target-mips
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
Reviewed-by: James Hogan
---
v4:
* remove OPC_SPECIAL35_RESERVED and OPC_SPECIAL37_RESERVED
v2:
* correct conditions to match instruction name
---
disas/mips.c| 8
target-mips/translate.c | 18 --
2
Use "R6_" prefix in front of all new Multiply / Divide instructions for
easier differentiation between R6 and preR6.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v2:
* use tcg_gen_mul_* for cases where the high part is discarded
---
disas/mips.c| 16 +++
t
, ALIGN and BITSWAP instructions
Leon Alrae (18):
target-mips: define ISA_MIPS64R6
target-mips: signal RI Exception on instructions removed in R6
target-mips: add SELEQZ and SELNEZ instructions
target-mips: move LL and SC instructions
target-mips: extract decode_opc_special* from
The encoding of LL and SC instruction has changed in MIPS32 Release 6.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
disas/mips.c|9 -
target-mips/translate.c | 29 +++--
2 files changed, 35 insertions(+), 3 deletions(-)
diff --git
functions will contain instructions which were removed in R6.
Signed-off-by: Leon Alrae
---
v2:
* imm contains shifted value
---
target-mips/translate.c | 227 +--
1 files changed, 159 insertions(+), 68 deletions(-)
diff --git a/target-mips/translate.
In R6 the special behaviour for data references is also specified for Kernel
and Supervisor mode. Therefore MIPS_HFLAG_UX is replaced by generic
MIPS_HFLAG_AWRAP indicating enabled 32-bit address wrapping.
Signed-off-by: Leon Alrae
---
v2:
* set hflag indicating 32-bit wrapping in compute_hflags
The encoding of PREF, CACHE, LLD and SCD instruction changed in MIPS32R6.
Additionally, the hint codes in PREF instruction greater than or
equal to 24 generate Reserved Instruction Exception.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
disas/mips.c|4
target
Also consider OPC_SPIM instruction as deleted in R6 because it is overlaping
with MIPS32R6 SDBBP.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v2:
* check_insn_opc_removed() moved to decode_opc_special2_legacy()
---
disas/mips.c|5 ++
target-mips/translate.c | 121
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v2:
* correct conditions to match instruction name
---
disas/mips.c|8
target-mips/translate.c | 16
2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
Use "R6_" prefix in front of all new Multiply / Divide instructions for
easier differentiation between R6 and preR6.
Signed-off-by: Leon Alrae
---
v2:
* use tcg_gen_mul_* for cases where the high part is discarded
---
disas/mips.c| 16 +++
target-mips/translat
Move DSP and Loongson instruction to *_legacy functions as they have been
removed in R6.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/translate.c | 195 ---
1 files changed, 98 insertions(+), 97 deletions(-)
diff --git a
.
Signed-off-by: Leon Alrae
---
disas/mips.c| 22 +++
target-mips/helper.h| 21 +++
target-mips/op_helper.c | 108 +++
target-mips/translate.c | 449 ++-
4 files changed, 552 insertions(+), 48 deletions(-)
diff --git a/disas
From: Yongbok Kim
Introduce MIPS32R6 Compact Branch instructions which do not have delay slot -
they have forbidden slot instead. However, current implementation does not
support forbidden slot yet.
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
v2:
* rename "handle_delay_slo
From: Yongbok Kim
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
v2:
* have separate bitswap and dbitswap helpers and use common function
* use TCG_CALL_NO_RWG_SE flag for bitswap and dbitswap helpers
* remove useless shift in ALIGN and DALIGN
* improve ALIGN implementation by
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 29 +
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 29dc2ef..0adbb19 100644
--- a/target-mips/translate_init.c
+++ b
Signed-off-by: Leon Alrae
---
disas/mips.c| 42 +-
target-mips/translate.c | 198 ---
2 files changed, 227 insertions(+), 13 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index bee39d8..e041858 100644
--- a/disas/mips.c
Status.FR bit must be ignored on write and read as 1 when an implementation of
Release 6 of the Architecture in which a 64-bit floating point unit is
implemented.
Signed-off-by: Leon Alrae
---
target-mips/translate.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a
Signed-off-by: Leon Alrae
---
v2:
* move new CPU definition to a separate patch
---
target-mips/mips-defs.h | 28 +++-
1 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index 9dfa516..6cb62b2 100644
--- a
From: Yongbok Kim
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
disas/mips.c|2 ++
target-mips/translate.c | 18 --
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index dd2473e..e3e253f 100644
--- a
From: Yongbok Kim
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
disas/mips.c| 44 ++
target-mips/helper.h| 27 ++
target-mips/op_helper.c | 111 +
target-mips/translate.c | 206
returns y if |y| > |x|,
otherwise maxnum(x,y)
Signed-off-by: Leon Alrae
---
fpu/softfloat.c | 37 +++--
include/fpu/softfloat.h |4
2 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softf
After selecting CPU in QEMU the base ISA will not change. Therefore
introducing *_arch function pointers that are set in cpu_state_reset to
point at the appropriate SPECIAL and SPECIAL3 decoding functions, and avoid
unnecessary 'if' statements.
Signed-off-by: Leon Alrae
---
t
JR has been removed in R6 and now this instruction will cause Reserved
Instruction Exception. Therefore use JALR with rd=0 which is equivalent to JR.
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/mips
loads / stores
- traps
- legacy accumulator instructions
- COP1X
- MIPS-3D
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/translate.c | 64 +--
1 files changed, 56 insertions(+), 8 deletions(-)
diff --git a/target-mips
On 11/06/2014 17:39, Richard Henderson wrote:
> On 06/11/2014 08:19 AM, Leon Alrae wrote:
>> * add missing zero register case
>
> What missing zero register case?
>
>> +if (rd == 0) {
>> +/* Treat as NOP. */
>> +break;
>>
tive_tc.CP0_UserLocal));
>> +rn = "UserLocal";
>> +} else {
>> +tcg_gen_movi_tl(arg, 0);
>> +}
>> default:
>> goto die;
>> }
You forgot to put "break" at the end of the case - this leads to
Reserved Instruction exception when trying to read the register.
Regards,
Leon
comments / suggestions are more than welcome!
Thanks,
Leon
Leon Alrae (12):
target-mips: add KScratch registers
target-mips: update cpu_save/cpu_load to support KScratch registers
target-mips: distinguish between data load and instruction fetch
target-mips: add RI and XI fields to TLB
CP0_KScratch1-6 registers.
For Release 6, all KScratch registers are required.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h |3 +++
target-mips/translate.c | 27 +++
2 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/target-mips/cpu.h b/target
In Revision 3 of the architecture, the RI and XI bits were added to the TLB
to enable more secure access of memory pages. These bits (along with the Dirty
bit) allow the implementation of read-only, write-only, no-execute access
policies for mapped pages.
Signed-off-by: Leon Alrae
---
target
is in a branch delay slot.
The BadInstr and BadInstrP registers are provided to allow acceleration of
instruction emulation.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h |6 +++
target-mips/helper.c| 23 +++
target-mips/translate.c | 102
when the virtual address of a memory load
reference matches a TLB entry whose RI bit is set. This exception type can
only occur if the RI bit is implemented within the TLB and is enabled, this is
denoted by the PageGrain RIE bit.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h|5
Signed-off-by: Leon Alrae
---
target-mips/helper.c | 27 ---
1 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 064622c..b59ac13 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -26,6 +26,12
support for Config4.IE == 3 only (i.e. TLBINV*
instructions operate on entire MMU).
Single TLB entry can be marked as invalid on TLB entry write by having
EntryHi.EHINV set to 1.
Signed-off-by: Leon Alrae
---
disas/mips.c |2 +
target-mips/cpu.h|7
target
PageGrain needs rw bitmask which differs between MIPS architectures.
In pre-R6 if RIXI is supported, PageGrain.XIE and PageGrain.RIE are writeable,
whereas in R6 they are read-only 1.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h|4
target-mips/helper.h |5
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 561eeb0..1f199fd 100644
--- a/target-mips/translate_init.c
+++ b/target-mips
Signed-off-by: Leon Alrae
---
target-mips/machine.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/target-mips/machine.c b/target-mips/machine.c
index 966c5ef..a51b344 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -26,6 +26,10 @@ static void
Execution of these instructions can trigger exceptions which are supposed
to update BadInstr/BadInstrP. Therefore saving cpu state in order capture
the opcode.
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions
Signed-off-by: Leon Alrae
---
target-mips/machine.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/target-mips/machine.c b/target-mips/machine.c
index 0496faa..966c5ef 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -144,6 +144,9 @@ void
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 1f199fd..0deaee7 100644
--- a/target-mips/translate_init.c
+++ b/target-mips
case OPC_DAHI:
>> +check_insn(ctx, ISA_MIPS32R6);
>> +check_mips_64(ctx);
>> +if (rs != 0) {
>> +tcg_gen_addi_i64(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm <<
>> 32);
>
> Small nitpicking: even if it is guarded by #ifdef, in theory the _tl
> type should be used there, to match the register type.
I'll correct it.
Thanks,
Leon
On 19/06/2014 23:16, Aurelien Jarno wrote:
> On Wed, Jun 11, 2014 at 04:19:52PM +0100, Leon Alrae wrote:
>> Signed-off-by: Leon Alrae
>> ---
>> target-mips/translate_init.c | 29 +
>> 1 files changed, 29 insertions(+), 0 deletions(-)
>
v, i32, i32, i32)
>> +DEF_HELPER_4(float_msubf_d, i64, env, i64, i64, i64)
>> +
>
> Why not using FOP_PROTO here?
>
I'll correct it.
Thanks,
Leon
On 11/06/2014 17:52, Richard Henderson wrote:
> On 06/11/2014 08:19 AM, Leon Alrae wrote:
>> +case OPC_BEQZC:
>> +tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, t0, 0);
>> +break;
> ...
>> +/* Compact branches don't have dela
ping
On 05/08/2014 10:26, Leon Alrae wrote:
> ping
>
> http://patchwork.ozlabs.org/patch/365066/
> http://patchwork.ozlabs.org/patch/365042/
> http://patchwork.ozlabs.org/patch/365046/
> http://patchwork.ozlabs.org/patch/365056/
> http://patchwork.ozlabs.org/patch/365059/
ping
Anybody? There hasn't been any feedback on this patchset for almost 2
months now...
On 12/08/2014 12:36, Leon Alrae wrote:
> ping
>
> On 05/08/2014 10:26, Leon Alrae wrote:
>> ping
>>
>> http://patchwork.ozlabs.org/patch/365066/
>> http://patc
These are not DSP instructions, thus there is no "ac" field.
For more details please refer to instruction encoding of
MULT, MULTU, MADD, MADDU, MSUB, MSUBU, MFHI, MFLO, MTHI, MTLO in
MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set
Signed-off-by:
On 03/08/13 23:01, Aurelien Jarno wrote:
> On Thu, Aug 01, 2013 at 11:02:27AM +0100, Leon Alrae wrote:
>> These are not DSP instructions, thus there is no "ac" field.
>>
>> For more details please refer to instruction encoding of
>> MULT, MULTU, MADD, MADDU, M
On 05/08/13 11:50, Aurelien Jarno wrote:
> On Mon, Aug 05, 2013 at 08:41:52AM +0100, Leon Alrae wrote:
>> On 03/08/13 23:01, Aurelien Jarno wrote:
>>> On Thu, Aug 01, 2013 at 11:02:27AM +0100, Leon Alrae wrote:
>>>> These are not DSP instructions, thus there is no
: The microMIPS32
Instruction Set
MIPS Architecture for Programmers Volume IV-e: The MIPS DSP Module for
the microMIPS32 Architecture
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 58 ++
1 files changed, 53 insertions(+), 5 deletions
: The microMIPS32
Instruction Set
MIPS Architecture for Programmers Volume IV-e: The MIPS DSP Module for
the microMIPS32 Architecture
Signed-off-by: Leon Alrae
---
Changes from v2:
Do not ignore bits 14 and 15 for case 0x35
Changes from v1:
Add DSP version of listed instructions
target-mips
In R6 the special behaviour for data references is also specified for Kernel
and Supervisor mode. Therefore MIPS_HFLAG_UX is replaced by generic
MIPS_HFLAG_AWRAP indicating enabled 32-bit address wrapping.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v2:
* set hflag indicating 32
Creating separate decode functions for special, special2 and special3
instructions to ease adding new R6 instructions and removing legacy
instructions.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/translate.c | 1678 ---
1
loads / stores
- traps
- legacy accumulator instructions
- COP1X
- MIPS-3D
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/translate.c | 64 ++---
1 file changed, 56 insertions(+), 8 deletions(-)
diff --git a/target-mips/translate.c
Also consider OPC_SPIM instruction as deleted in R6 because it is overlaping
with MIPS32R6 SDBBP.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v2:
* check_insn_opc_removed() moved to decode_opc_special2_legacy()
---
disas/mips.c| 5 ++
target-mips/translate.c | 121
Signed-off-by: Leon Alrae
---
v3:
* use sextract32 instead of open coding the bit field extraction
* replace _i64 with _tl in DAHI, DATI and DAUI
* fix misleading LDPC comment
---
disas/mips.c| 42 ++-
target-mips/translate.c | 197
functions will contain instructions which were removed in R6.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v2:
* imm contains shifted value
---
target-mips/translate.c | 228 +---
1 file changed, 160 insertions(+), 68 deletions(-)
diff --gi
Status.FR bit must be ignored on write and read as 1 when an implementation of
Release 6 of the Architecture in which a 64-bit floating point unit is
implemented.
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
v3:
* remove line modifying CP0_Status_rw_bitmask as this is done while
returns y if |y| > |x|,
otherwise maxnum(x,y)
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v3:
* rename abs argument to ismag
---
fpu/softfloat.c | 37 +++--
include/fpu/softfloat.h | 4
2 files changed, 35 insertions(+),
Signed-off-by: Leon Alrae
---
v3:
* add comment to make it clear that the current definition of MIPS64R6-generic
CPU does not contain support for all MIPS64R6 features yet.
---
target-mips/translate_init.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a
From: Yongbok Kim
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v3:
* bitswap: use gen_load_gpr instead of optimizing very unlikely case and
making it less readable
v2:
* have separate bitswap and dbitswap helpers and use common function
* use
JR has been removed in R6 and now this instruction will cause Reserved
Instruction Exception. Therefore use JALR with rd=0 which is equivalent to JR.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
hw/mips/mips_malta.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions
From: Yongbok Kim
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
disas/mips.c| 2 ++
target-mips/translate.c | 18 --
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index 9d13bc0
From: Yongbok Kim
Introduce MIPS32R6 Compact Branch instructions which do not have delay slot -
they have forbidden slot instead. However, current implementation does not
support forbidden slot yet.
Add also BC1EQZ and BC1NEZ instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
From: Yongbok Kim
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
disas/mips.c| 44 +++
target-mips/helper.h| 27 +++
target-mips/op_helper.c | 111 ++
target-mips/translate.c | 206
.
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
v4:
* in gen_sel_d and gen_sel_s: do not 'return' on invalid instruction, so temps
are always freed
* fix style issue
v3:
* use FOP_PROTO for new instructions and create FLOAT_RINT macro to be
consistent
* use TCG_CALL_NO_RWG_S
HELPER_ST(sd, stq, uint64_t)
> +#endif
> +#undef HELPER_ST
> +
I'm not sure if moving this to cpu.h is a good idea - it won't be used
anywhere else than in op_helper.c and msa_helper.c (and probably these
static inlines will generate warnings in clang). Only msa_ld_df and
msa_st_df in msa_helper.c need them, thus in my opinion it will be
better just to move these 2 functions from msa_helper.c to op_helper.c.
Regards,
Leon
LPER_ST(st16, stw, uint16_t)
> +HELPER_ST(st32, stl, int32_t)
> +HELPER_ST(st64, stq, int64_t)
> #undef HELPER_ST
>
> #endif /* !defined (__MIPS_CPU_H__) */
>
do_ld8, do_ld32 and do_ld64 are duplications of existing do_lbu, do_lw
and do_ld. Similarily with do_st*.
Leon
+OPC_MSA_FSOR_df = (0x9 << 22) | OPC_MSA_3RF_1C,
> +OPC_MSA_FSEQ_df = (0xA << 22) | OPC_MSA_3RF_1A,
> +OPC_MSA_FTQ_df = (0xA << 22) | OPC_MSA_3RF_1B,
> +OPC_MSA_FSUNE_df= (0xA << 22) | OPC_MSA_3RF_1C,
> +OPC_MSA_FSUEQ_df= (0xB << 22) | OPC_MSA_3RF_1A,
> +OPC_MSA_FSNE_df = (0xB << 22) | OPC_MSA_3RF_1C,
> +OPC_MSA_FSLT_df = (0xC << 22) | OPC_MSA_3RF_1A,
> +OPC_MSA_FMIN_df = (0xC << 22) | OPC_MSA_3RF_1B,
> +OPC_MSA_MULR_Q_df = (0xC << 22) | OPC_MSA_3RF_1C,
> +OPC_MSA_FSULT_df= (0xD << 22) | OPC_MSA_3RF_1A,
> +OPC_MSA_FMIN_A_df = (0xD << 22) | OPC_MSA_3RF_1B,
> +OPC_MSA_MADDR_Q_df = (0xD << 22) | OPC_MSA_3RF_1C,
> +OPC_MSA_FSLE_df = (0xE << 22) | OPC_MSA_3RF_1A,
> +OPC_MSA_FMAX_df = (0xE << 22) | OPC_MSA_3RF_1B,
> +OPC_MSA_MSUBR_Q_df = (0xE << 22) | OPC_MSA_3RF_1C,
> +OPC_MSA_FSULE_df= (0xF << 22) | OPC_MSA_3RF_1A,
> +OPC_MSA_FMAX_A_df = (0xF << 22) | OPC_MSA_3RF_1B,
> +
> +/* BIT instruction df(bits 22..16) = _B _H _W _D */
> +OPC_MSA_SLLI_df = (0x0 << 23) | OPC_MSA_BIT_09,
> +OPC_MSA_SAT_S_df= (0x0 << 23) | OPC_MSA_BIT_0A,
> +OPC_MSA_SRAI_df = (0x1 << 23) | OPC_MSA_BIT_09,
> +OPC_MSA_SAT_U_df= (0x1 << 23) | OPC_MSA_BIT_0A,
> +OPC_MSA_SRLI_df = (0x2 << 23) | OPC_MSA_BIT_09,
> +OPC_MSA_SRARI_df= (0x2 << 23) | OPC_MSA_BIT_0A,
> +OPC_MSA_BCLRI_df= (0x3 << 23) | OPC_MSA_BIT_09,
> +OPC_MSA_SRLRI_df= (0x3 << 23) | OPC_MSA_BIT_0A,
> +OPC_MSA_BSETI_df= (0x4 << 23) | OPC_MSA_BIT_09,
> +OPC_MSA_BNEGI_df= (0x5 << 23) | OPC_MSA_BIT_09,
> +OPC_MSA_BINSLI_df = (0x6 << 23) | OPC_MSA_BIT_09,
> +OPC_MSA_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09,
> +};
> +
> /* global register indices */
> static TCGv_ptr cpu_env;
> static TCGv cpu_gpr[32], cpu_PC;
>
Otherwise it looks good to me:
Reviewed-by: Leon Alrae
Leon
On 14/07/2014 10:55, Yongbok Kim wrote:
> add msa_helper.c
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/Makefile.objs |2 +-
> target-mips/msa_helper.c | 196
> +
> 2 files changed, 197 insertions(+), 1 deletions(-)
> create mode 100644 t
op1 == OPC_MSA_BZ_H ||
> + op1 == OPC_MSA_BZ_W ||
> + op1 == OPC_MSA_BZ_D ||
> + op1 == OPC_MSA_BNZ_B ||
> + op1 == OPC_MSA_BNZ_H ||
> + op1 == OPC_MSA_BNZ_W ||
> + op1 == OPC_MSA_BNZ_D)) {
> +gen_msa_branch(env, ctx, op1);
can't this be merged into the switch below?
> +} else if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
> check_cp1_enabled(ctx);
> -op1 = MASK_CP1(ctx->opcode);
> +
> switch (op1) {
> case OPC_MFHC1:
> case OPC_MTHC1:
>
Regards,
Leon
111011.rs.1.<--imm16> ALUIPC
I couldn't come up with better name having reasonable length, any
suggestions are welcome.
Thanks,
Leon
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/mips-defs.h | 28 +++-
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index 9dfa516..6cb62b2 100644
--- a/target-mips/mips-defs.h
+++ b
Hi,
This pull request has been assembled from pending target-mips patches which
look good to me and received in my opinion sufficient review comments. They
were tested mainly in context of MIPS. Please have a look and pull.
Thanks,
Leon
Cc: Peter Maydell
Cc: Aurelien Jarno
The following
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
Reviewed-by: James Hogan
---
disas/mips.c| 8
target-mips/translate.c | 18 --
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index 2106b57..b950e53 100644
The encoding of PREF, CACHE, LLD and SCD instruction changed in MIPS32R6.
Additionally, the hint codes in PREF instruction greater than or
equal to 24 generate Reserved Instruction Exception.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
disas/mips.c| 4
target
In R6 the special behaviour for data references is also specified for Kernel
and Supervisor mode. Therefore MIPS_HFLAG_UX is replaced by generic
MIPS_HFLAG_AWRAP indicating enabled 32-bit address wrapping.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/cpu.h | 18
Creating separate decode functions for special, special2 and special3
instructions to ease adding new R6 instructions and removing legacy
instructions.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/translate.c | 1678 ---
1
loads / stores
- traps
- legacy accumulator instructions
- COP1X
- MIPS-3D
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/translate.c | 64 ++---
1 file changed, 56 insertions(+), 8 deletions(-)
diff --git a/target-mips/translate.c
The encoding of LL and SC instruction has changed in MIPS32 Release 6.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
Reviewed-by: James Hogan
---
disas/mips.c| 9 -
target-mips/translate.c | 28 ++--
2 files changed, 34 insertions(+), 3
Use "R6_" prefix in front of all new Multiply / Divide instructions for
easier differentiation between R6 and preR6.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
disas/mips.c| 16 +++
target-mips/translate.c | 343 +
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