This patch series implement set of features whose presence became mandatory in MIPS64R6: - KScratch registers, - Read-Inhibit and Execute-Inhibit page protection bits, - TLB Invalidate (TLBINV and TLBINVF instructions), - BadInstr and BadInstrP. The last patch in the series enables them in MIPS64R6 CPU config therefore this series should be applied on the top of pending patches introducing MIPS64R6 Instruction Set.
Commits briefly describe each feature. For more details please refer to the Volume III (The MIPS64 and microMIPS64 Privileged Resource Architecture) and Volume II (The MIPS64 Instruction Set) of MIPS documents available at: http://www.imgtec.com/mips/architectures/mips64.asp This patchset focuses on features which existed before Release 6. It does not contain new MIPS64R6 features like forbidden slot, SBRI, reserved fields. This will come as a separate patchset soon. Any comments / suggestions are more than welcome! Thanks, Leon Leon Alrae (12): target-mips: add KScratch registers target-mips: update cpu_save/cpu_load to support KScratch registers target-mips: distinguish between data load and instruction fetch target-mips: add RI and XI fields to TLB entry target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1} target-mips: add new Read-Inhibit and Execute-Inhibit exceptions target-mips: add TLBINV support target-mips: add BadInstr and BadInstrP support target-mips: save cpu state if instruction can cause an exception target-mips: update cpu_save/cpu_load to support BadInstr registers target-mips: enable features in MIPS32R5-generic core target-mips: enable features in MIPS64R6-generic core disas/mips.c | 2 + target-mips/cpu.h | 36 ++++++++- target-mips/helper.c | 88 ++++++++++++++++--- target-mips/helper.h | 7 ++ target-mips/machine.c | 16 ++++ target-mips/op_helper.c | 98 +++++++++++++++++++-- target-mips/translate.c | 196 ++++++++++++++++++++++++++++++++++++++++-- target-mips/translate_init.c | 20 ++++- 8 files changed, 427 insertions(+), 36 deletions(-) -- 1.7.5.4
