Hi, This pull request has been assembled from pending target-mips patches which look good to me and received in my opinion sufficient review comments. They were tested mainly in context of MIPS. Please have a look and pull.
Thanks, Leon Cc: Peter Maydell <peter.mayd...@linaro.org> Cc: Aurelien Jarno <aurel...@aurel32.net> The following changes since commit b1d28ec6a7dbdaadda39d29322f0de694aeb0b74: Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20141010' into staging (2014-10-10 14:55:29 +0100) are available in the git repository at: git://github.com/lalrae/qemu.git tags/mips-20141015 for you to fetch changes up to 340fff722d8a7cf9c0d4f1e1b4fad03a145a9657: target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX (2014-10-14 13:29:15 +0100) ---------------------------------------------------------------- MIPS patches 2014-10-15 Changes: * MIPS64R6 (unprivileged) support * fix for broken MIPS16 and microMIPS * SYNCI improvement * unused MIPS code removal ---------------------------------------------------------------- Dongxue Zhang (1): target-mips/translate.c: Update OPC_SYNCI Leon Alrae (17): target-mips: define ISA_MIPS64R6 target-mips: signal RI Exception on instructions removed in R6 target-mips: add SELEQZ and SELNEZ instructions target-mips: move LL and SC instructions target-mips: extract decode_opc_special* from decode_opc target-mips: split decode_opc_special* into *_r6 and *_legacy target-mips: signal RI Exception on DSP and Loongson instructions target-mips: move PREF, CACHE, LLD and SCD instructions target-mips: redefine Integer Multiply and Divide instructions target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6 target-mips: Status.UX/SX/KX enable 32-bit address wrapping target-mips: add AUI, LSA and PCREL instruction families softfloat: add functions corresponding to IEEE-2008 min/maxNumMag target-mips: add new Floating Point instructions target-mips: do not allow Status.FR=0 mode in 64-bit FPU mips_malta: update malta's pseudo-bootloader - replace JR with JALR target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA Peter Maydell (5): target-mips/dsp_helper.c: Remove unused function get_DSPControl_24() target-mips/op_helper.c: Remove unused do_lbu() function target-mips/translate.c: Add ifdef guard around check_mips64() target-mips/dsp_helper.c: Add ifdef guards around various functions target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX Yongbok Kim (5): target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions target-mips: add compact and CP1 branches target-mips: add new Floating Point Comparison instructions target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions target-mips: fix broken MIPS16 and microMIPS disas/mips.c | 211 ++- fpu/softfloat.c | 37 +- hw/mips/mips_malta.c | 10 +- include/fpu/softfloat.h | 4 + target-mips/cpu.h | 31 +- target-mips/dsp_helper.c | 26 +- target-mips/helper.h | 52 + target-mips/mips-defs.h | 28 +- target-mips/op_helper.c | 239 ++- target-mips/translate.c | 4114 ++++++++++++++++++++++++++++++------------ target-mips/translate_init.c | 30 + 11 files changed, 3563 insertions(+), 1219 deletions(-)
