On 3/21/25 11:42, Philippe Mathieu-Daudé wrote:
The CPU_RESOLVING_TYPE definition was added in commit
0dacec874fa ("cpu: add CPU_RESOLVING_TYPE macro"), but
then added again in commit d3ae32d4d20. Remove the
duplication.
Fixes: d3ae32d4d20 ("target/hppa: Implement cpu_list")
Signed-off-by: Phili
On 3/17/25 8:10 PM, Nicolin Chen wrote:
> On Mon, Mar 17, 2025 at 07:07:52PM +0100, Eric Auger wrote:
>> On 3/17/25 6:54 PM, Nicolin Chen wrote:
>>> On Wed, Mar 12, 2025 at 04:15:10PM +0100, Eric Auger wrote:
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> Based on SMMUv3 as a parent dev
On 3/20/25 15:29, Pierrick Bouvier wrote:
This define is used only in accel/kvm/kvm-all.c, so we push directly the
definition there. Add more visibility to kvm_arch_on_sigbus_vcpu() to
allow removing this define from any header.
The architectures defining KVM_HAVE_MCE_INJECTION are i386, x86_64
From: Richard Henderson
Do not unconditionally attempt to read 4 bytes, as there
may only be 2 bytes remaining in the translator cache.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20250325224403.401
Temporary variable ret is assigned at last line and return, it can
be removed and return directly.
Signed-off-by: Bibo Mao
Reviewed-by: Markus Armbruster
Reviewed-by: Philippe Mathieu-Daudé
---
target/loongarch/tcg/tlb_helper.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff -
The FDT does not normally store name properties but reconstructs it
from path but each node in Open Firmware should at least have this
property. This is correctly handled in getprop but nextprop should
also return it even if not present as a property. This patch fixes
that and also skips phandle wh
Overview
=
Implemented Firmware Assisted Dump (fadump) on PSeries machine in QEMU.
Fadump is an alternative dump mechanism to kdump, in which we the firmware
does a memory preserving boot, and the second/crashkernel is booted fresh
like a normal system reset, instead of the crashed kernel
Adding Cindy and Eugenio
On Thu, Mar 20, 2025 at 12:34 AM Konstantin Shkolnyy wrote:
>
> I’m observing a problem while testing VDPA with Nvidia ConnectX-6 (mlx5)
> on s390.
>
> Upon start, virtio_net_device_realize() tries to set a new MAC address
> by VHOST_VDPA_SET_CONFIG which doesn’t do anyth
A few functions now end with a label. The next commit will clean them
up.
Signed-off-by: Markus Armbruster
---
include/system/os-win32.h | 1 -
target/ppc/kvm_ppc.h| 3 ---
accel/tcg/cpu-exec.c| 1 -
block/gluster.c | 4
blo
On Wed, Mar 19, 2025 at 5:08 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 3/18/25 1:42 PM, Peter Maydell wrote:
> > On Fri, 7 Mar 2025 at 12:46, Daniel Henrique Barboza
> > wrote:
> >>
> >> Coverity found the following issue:
> >>
> >>>>> CID 1593156: Integer handling issues (OVERFLOW_B
On 3/21/25 10:26, Jamin Lin wrote:
According to the AST2700 design, the data source address is 64-bit, with
R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0].
Similarly, the digest address is 64-bit, with R_HASH_DEST_HI storing bits
[63:32] and R_HASH_DEST storing bits [31:0]
Peter Xu writes:
> On Thu, Mar 20, 2025 at 11:45:29AM -0300, Fabiano Rosas wrote:
>> There's a bunch of other issues as well:
>>
>> - no clear distinction between what should go in the header and what
>> should go in the packet.
>>
>> - the header taking up one slot in the iov, which should i
On 3/14/25 15:48, Steven Sistare wrote:
On 3/14/2025 10:25 AM, Cédric Le Goater wrote:
John,
+Steven, for the Live upsate series.
On 2/19/25 15:48, John Levon wrote:
This is the 8th revision of the vfio-user client implementation. The vfio-user
protocol allows for implementing (PCI) devices
Currently the boot.S code assumes everything starts at EL1. This will
break things like the memory test which will barf on unaligned memory
access when run at a higher level.
Adapt the boot code to do some basic verification of the starting mode
and the minimal configuration to move to the lower e
Accept "... lorem ipsum ..." in addition to "...".
Signed-off-by: Markus Armbruster
---
docs/devel/qapi-code-gen.rst| 6 --
docs/sphinx/qmp_lexer.py| 2 +-
tests/qapi-schema/doc-good.json | 2 +-
tests/qapi-schema/doc-good.out | 2 +-
tests/qapi-schema/doc-good.txt | 2 +-
5 f
Fix copy/paste error writing to the ATU_UPPER_TARGET
register, we want to update the upper 32 bits.
Cc: qemu-sta...@nongnu.org
Reported-by: Joey
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2861
Fixes: d64e5eabc4c ("pci: Add support for Designware IP block")
Signed-off-by: Philippe Mat
Introduce the QOM arm_cpu_is_64bit() helper, which checks
whether a vCPU parent class is TYPE_AARCH64_CPU. Use it in
arm_cpu_initfn() to remove a TARGET_AARCH64 definition use.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 27 +--
1 file changed, 17 inserti
This series is similar to the TARGET_SUPPORTS_MTTCG replacement
to a 'mttcg_supported' field in TCGCPUOps, but doing it for
TARGET_HAS_PRECISE_SMC, adding the 'has_precise_smc' field.
Based on tcg-next tree.
Philippe Mathieu-Daudé (2):
tcg: Introduce and use target_has_precise_smc() runtime hel
target_has_precise_smc() returns the value of the
TARGET_HAS_PRECISE_SMC definition at runtime.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tb-internal.h | 3 +++
accel/tcg/cpu-exec.c| 9 +
accel/tcg/tb-maint.c| 18 +-
accel/tcg/user-exec.c | 10 +-
Instead of having a compile-time TARGET_HAS_PRECISE_SMC definition,
have targets set the 'has_precise_smc' field in the TCGCPUOps
structure.
Since so far we only emulate one target architecture at a time,
add a static 'tcg_target_has_precise_smc' variable, initialized
just after calling TCGCPUOps:
Hi Richard,
On 4/4/25 00:04, Philippe Mathieu-Daudé wrote:
By directly using TCGCPUOps::guest_default_memory_order,
we don't need the TCG_GUEST_DEFAULT_MO definition anymore.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Reviewed-by: Richard Henderson
Reviewed-by: Pierri
On Fri, 4 Apr 2025, Alexey Kardashevskiy wrote:
On Tue, 1 Apr 2025, at 01:26, BALATON Zoltan wrote:
The FDT does not normally store name properties but reconstructs it
from path but each node in Open Firmware should at least have this
property. This is correctly handled in getprop but nextprop s
On 4/4/25 14:56, Philippe Mathieu-Daudé wrote:
+Paolo
On 4/4/25 20:23, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Currently hvf_enabled() is restricted to target-specific code.
By defining CONFIG_HVF_IS_POSSIBLE we allow its use anywhere.
Instead, we can simply m
On 18/03/2025 09:54, Cédric Le Goater wrote:
> vfio_devices_query_dirty_bitmap() is only used in "dirty-tracking.c".
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joao Martins
> ---
> hw/vfio/dirty-tracking.h | 3 ---
> hw/vfio/dirty-tracking.c | 2 +-
> 2 files changed, 1 insertion(+), 4
On 4/4/25 14:53, Philippe Mathieu-Daudé wrote:
On 4/4/25 20:20, Pierrick Bouvier wrote:
On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
We would like to get rid of '-I target/$ARCH/' in the CPPFLAGS.
While this change is correct, this is not strictly needed.
With the current approach, using a
On 4/4/25 14:54, Philippe Mathieu-Daudé wrote:
On 4/4/25 20:21, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Extract PSCI definitions (which are not target specific)
to the new "target/arm/psci.h", so code from hw/arm/ can
use them without having to include the target
On 4/4/25 15:00, Philippe Mathieu-Daudé wrote:
+Paolo
On 4/4/25 20:25, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Hardware accelerators depends on the host, not the guest.
While this is true, no we can't unpoison those define.
They are applied per target, and not
On 4/4/25 15:05, Philippe Mathieu-Daudé wrote:
On 4/4/25 20:28, Pierrick Bouvier wrote:
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Replace the target-specific TARGET_AARCH64 definition
by a call to the generic target_long_bits() helper.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/
address_with_allocation_tag() is only used in mte_helper.c,
move it there.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/internals.h | 5 -
target/arm/tcg/mte_helper.c | 5 +
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/in
"tcg/mte_helper.h" header name is a bit misleading, since it
isn't restricted to TCG helpers. Rename it as "tcg/mte.h"
which is a bit more generic.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/{mte_helper.h => mte.h} | 0
target/arm/gdbstub64.c | 2 +-
target/arm/tcg/
We'd like to reduce the use on TARGET_$arch definitions.
This series convert few to runtime checks, mostly in
MTE and gdbstub.
Philippe Mathieu-Daudé (9):
target/arm: Remove uses of TARGET_AARCH64 in arch_dump.c
target/arm: Remove use of TARGET_AARCH64 in dump.c
target/arm: Remove use of TAR
Some headers are indirectly pulled in. Make their inclusion
explicit, otherwise next commit triggers:
target/arm/tcg/mte_helper.c:188:26: error: call to undeclared function
'GETPC' [-Wimplicit-function-declaration]
188 | do_stg(env, ptr, xt, GETPC(), store_tag1);
|
On Wed, Apr 02, 2025 at 02:31:01AM -0700, Pinku Deb Nath wrote:
> Full Unit Access (FUA) is an optimization where a disk write with the
> flag set will be persisted to disk immediately instead of potentially
> remaining in the disk's write cache. This commit address the todo task
> for using pwrite
On 3/21/25 10:26, Jamin Lin wrote:
The digest_addr is set to "src_addr + 0x100", where src_addr is the DRAM
base address. However, the value 0x100 (16MB) is too large because the
AST1030 does not support DRAM, and its SRAM size is only 768KB.
A range size of 0x1000 (64KB) is sufficient f
According to the AST2700 design, the data source address is 64-bit, with
R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0].
Similarly, the digest address is 64-bit, with R_HASH_DEST_HI storing bits
[63:32] and R_HASH_DEST storing bits [31:0]. The HMAC key buffer address is also
The comments for segment_size and allocation_unit_size incorrectly
described them as 4KB. According to the UFS specification,
segment_size is expressed in units of 512 bytes.
Given segment_size = 0x2000 (8192), the actual size is 4MB.
Similarly, allocation_unit_size = 1 means 1 segment = 4MB.
This
On 3/23/25 08:41, Philippe Mathieu-Daudé wrote:
On 21/3/25 18:31, Pierrick Bouvier wrote:
Adding proper functions definition instead of macros, and eliminating
ifdefs is not really boilerplate.
In another thread Richard said for these cases we should use _Generic()
more.
I was thinking abo
The Aarch64 gdbstub code is guarded by checks on ARM_FEATURE_AARCH64
and isar_feature_aa64_sve(), only enabled for Aarch64 CPUs.
Remove TARGET_AARCH64 #ifdef'ry and build gdbstub64.c once.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/internals.h | 2 +-
target/arm/gdbstub.c | 4
t
It is safe to remove TARGET_AARCH64 #ifdef'ry for code
guarded by runtime check on aa64_sve ISA feature, which
is only available for Aarch64 CPUs.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/target/arm/cpu.c b/target/
On 4/4/25 08:27, Daniel Henrique Barboza wrote:
Using 'max' as
default CPU is done by other QEMU archs like aarch64 so we'll be more
compatible with everyone else.
This isn't true. qemu-system-aarch64 -M virt defaults to cortex-a15 (for hysterical
raisins), which is completely and totally use
The CPU_RESOLVING_TYPE definition was added in commit
0dacec874fa ("cpu: add CPU_RESOLVING_TYPE macro"), but
then added again in commit d3ae32d4d20. Remove the
duplication.
Fixes: d3ae32d4d20 ("target/hppa: Implement cpu_list")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Move MTE declarations out of "internals.h" to TCG "mte.h".
Include "mte.h" when necessary.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/internals.h | 121
target/arm/tcg/mte.h | 124
target/arm/tcg/sve_ldst_internal.h |
It is safe to remove TARGET_AARCH64 #ifdef'ry for code
guarded by runtime check on aa64_sve ISA feature, which
is only available for Aarch64 CPUs.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/arch_dump.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/arm/arch_dump.c b/ta
On 1/4/25 10:34, Nicholas Piggin wrote:
On Tue Apr 1, 2025 at 5:51 AM AEST, Richard Henderson wrote:
On 3/31/25 10:54, Nicholas Piggin wrote:
Add an option TARGET_HAS_LAZY_ICACHE that does not invalidate TBs upon
store, but instead tracks that the icache has become incoherent, and
provides a tb
If the dont-log flag is set in the 'timer use' field for the
'set watchdog' command, a watchdog timeout will not get logged as
a timer use expiration.
Signed-off-by: Nicholas Piggin
---
hw/ipmi/ipmi_bmc_sim.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/ipmi/ipmi_
On Tue, 11 Mar 2025 at 21:44, wrote:
> From: Marc-André Lureau
>
> Fixes: https://issues.redhat.com/browse/RHEL-81894
> Signed-off-by: Marc-André Lureau
* No commit message? Same for patch 09/10.
---
- Prasad
Zhenzhong,
Hi!
Eric asked me to review this series.
Since it's rather late since you posted will summarize review feedback
below/bottom.
- Don
On 2/19/25 3:22 AM, Zhenzhong Duan wrote:
Hi,
Per Jason Wang's suggestion, iommufd nesting series[1] is split into
"Enable stage-1 translation for em
Match the prototype of cpu_memory_rw_debug().
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 2 +-
target/sparc/cpu.h| 2 +-
target/sparc/mmu_helper.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
in
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/exynos4210.c | 1 -
hw/arm/highbank.c | 1 -
hw/arm/mps3r.c | 1 -
hw/arm/smmuv3.c | 1 -
4 files changed, 4 deletions(-)
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index b452470598b..04439364370 100644
--- a/hw/arm/exynos42
On Wed, 2 Apr 2025, Bernhard Beschow wrote:
Am 31. März 2025 09:18:05 UTC schrieb "Daniel P. Berrangé"
:
General conceptual question . I've never understood what the dividing
line is between use of 'qemu_log_mask' and trace points.
I *think* it's the perspective: If you want to see any i
On 19/3/25 19:22, Alex Bennée wrote:
For some of the helpers we need a temporary variable to copy from
although we could add some helpers to return pointers into env in
those cases if we wanted to.
Signed-off-by: Alex Bennée
---
target/arm/gdbstub64.c | 53 ++--
On 23/3/25 18:37, Richard Henderson wrote:
Prepare for offset_io being non-zero in do_stb.
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On 2/19/25 15:48, John Levon wrote:
From: Jagannathan Raman
Instead of requesting region information on demand with
VFIO_DEVICE_GET_REGION_INFO, maintain a cache: this will become
necessary for performance for vfio-user, where this call becomes a
message over the control socket, so is of higher
On Thu, 27 Mar 2025 at 20:03, Marco Cavenati wrote:
> Enable the use of the mapped-ram migration feature with savevm/loadvm
> snapshots by adding the QIO_CHANNEL_FEATURE_SEEKABLE feature to
> QIOChannelBlock. Implement io_preadv and io_pwritev methods to provide
> positioned I/O capabilities that
Hello Prasad,
On Friday, April 04, 2025 10:19 CEST, Prasad Pandit wrote:
> * IIUC, when _FEATURE_SEEKABLE is set, the channel I/O sequence
> eventually makes underlying preadv(2)/pwritev(2) calls, which use
> lseek(2) to adjust the stream r/w pointer with the given offset,
> before doing the r/w
Signed-off-by: Philippe Mathieu-Daudé
---
target/tricore/translate.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 7cd26d8eaba..ad959f3b0a1 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/transl
Hello,
On 4/2/25 11:14, Kane-Chen-AS wrote:
This patch introduces part of the Secure Boot Controller device,
which consists of several sub-components, including an OTP memory,
OTP controller, cryptographic engine, and boot controller.
In this version, the implementation includes the OTP memory
On Fri, 21 Mar 2025 11:12:55 +0800
Bibo Mao wrote:
> In function virt_cpu_plug(), it will send cpu plug message to interrupt
> controller extioi and ipi irqchip. If there is problem in this function,
> system should continue to run and keep state the same before cpu is
> added.
_plug is not sup
Signed-off-by: Markus Armbruster
---
docs/devel/qapi-code-gen.rst | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/docs/devel/qapi-code-gen.rst b/docs/devel/qapi-code-gen.rst
index ad517349fc..25a46fafb6 100644
--- a/docs/devel/qapi-code-gen.rst
+++ b/d
The introduction explains example notation. The series merged in
merge commit e6485190f77e (in 9.1) improved how they look in generated
docs, but neglected to update the introduction accordingly. Do that
now.
Signed-off-by: Markus Armbruster
---
qapi/qapi-schema.json | 6 +++---
1 file changed
The "QEMU Guest Agent Protocol Reference" starts with the following
table of contents:
Contents
* QEMU Guest Agent Protocol Reference
* QEMU guest agent protocol commands and structs
This is useless. Delete the entire TOC.
Signed-off-by: Markus Armbruster
---
docs/interop/qemu
Contents adapted from qapi/qapi-schema.json.
Signed-off-by: Markus Armbruster
---
qga/qapi-schema.json | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/qga/qapi-schema.json b/qga/qapi-schema.json
index 35ec0e7db3..5316bfacbf 100644
--- a/qga/qapi-schema.j
The command can return any number of RockerOfDpaFlow objects. The
example shows it returning exactly two, with the second objecy's
members elided. Tweak it so it elides elements after the first
instead.
Signed-off-by: Markus Armbruster
---
qapi/rocker.json | 2 +-
1 file changed, 1 insertion(+
Markus Armbruster (11):
docs/devel/qapi-code-gen: Tidy up whitespace
qapi/rocker: Tidy up query-rocker-of-dpa-flows example
docs/interop: Delete "QEMU Guest Agent Protocol Reference" TOC
docs/interop: Sanitize QMP reference manuals TOC
docs/devel/qapi-code-gen: Improve the part on qmp-exa
The "QEMU QMP Reference Manual" and the "QEMU Storage Daemon QMP
Reference Manual" start with a table of contents that looks like this:
Contents
* Title of the manual
* Title of first first-level section
* Title of its first second-level section
* Title of its second
Contents adapted from qapi/qapi-schema.json.
Signed-off-by: Markus Armbruster
---
storage-daemon/qapi/qapi-schema.json | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/storage-daemon/qapi/qapi-schema.json
b/storage-daemon/qapi/qapi-schema.json
index 2a
On Friday, April 04, 2025 12:14 CEST, Prasad Pandit wrote:
> * If the r/w pointer adjustment (lseek(2)) is not required, then why
> set the '*_FEATURE_SEEKABLE' flag?
The QIO_CHANNEL_FEATURE_SEEKABLE flag is set to indicate that
the channel supports seekable operations. This flag is more about
Commit 5b4beba124 ("RISC-V Spike Machines") added the Spike machine and
made it default for qemu-system-riscv32/64. It was the first RISC-V
machine added in QEMU so setting it as default was sensible.
Today we have 7 riscv64 and 6 riscv32 machines and having 'spike' as
default machine is not intui
Full Unit Access (FUA) is an optimization where a disk write with the
flag set will be persisted to disk immediately instead of potentially
remaining in the disk's write cache. This commit address the todo task
for using pwritev2() with RWF_DSYNC in the thread pool section of
raw_co_prw(), if pwrit
On 27.03.25 15:47, Stefan Hajnoczi wrote:
On Tue, Mar 25, 2025 at 05:06:35PM +0100, Hanna Czenczek wrote:
Polling in I/O functions can lead to nested read_from_fuse_export()
"Polling" means several different things. "aio_poll()" or "nested event
loop" would be clearer.
Sure!
calls, overwrit
On 01.04.25 15:55, Eric Blake wrote:
On Tue, Mar 25, 2025 at 05:06:48PM +0100, Hanna Czenczek wrote:
Pull setting up and tearing down the AIO context handlers into two
dedicated functions.
Signed-off-by: Hanna Czenczek
---
block/export/fuse.c | 32
1 file ch
On 4/4/25 2:50 AM, Alistair Francis wrote:
On Fri, Mar 28, 2025 at 2:16 AM Philippe Mathieu-Daudé
wrote:
On 27/3/25 14:02, Daniel Henrique Barboza wrote:
Commit 5b4beba124 ("RISC-V Spike Machines") added the Spike machine and
made it default for qemu-system-riscv32/64. It was the first RIS
On 01.04.25 16:35, Eric Blake wrote:
On Tue, Mar 25, 2025 at 05:06:51PM +0100, Hanna Czenczek wrote:
Manually read requests from the /dev/fuse FD and process them, without
using libfuse. This allows us to safely add parallel request processing
in coroutines later, without having to worry about
On 04.04.25 09:20, Markus Armbruster wrote:
Vladimir Sementsov-Ogievskiy writes:
For change, pause, resume, complete, dismiss and finalize actions
corresponding job- and block-job commands are almost equal. The
difference is in find_block_job_locked() vs find_job_locked()
functions. What's dif
On Thu, Mar 27, 2025 at 02:53:24PM +0800, Haoqian He wrote:
2025年3月25日 17:51，Stefano Garzarella 写道：
On Tue, Mar 25, 2025 at 04:39:46PM +0800, Haoqian He wrote:
2025年3月24日 22:31，Stefano Garzarella 写道：
On Thu, Mar 20, 2025 at 08:21:30PM +0800, Haoqian He wrote:
2025年3月19日 23:20，Stefano Garza
Sorry, replied too early. :)
On 01.04.25 16:35, Eric Blake wrote:
On Tue, Mar 25, 2025 at 05:06:51PM +0100, Hanna Czenczek wrote:
Manually read requests from the /dev/fuse FD and process them, without
using libfuse. This allows us to safely add parallel request processing
in coroutines later,
We don't expect to hit exceptions in our testing so currently all the
vectors report an un-expected exception and then attempt to exit.
However for aarch64 we should always use the extended information
block as we do in _exit. Rather than duplicate the code on the error
handler just branch to the _
Hi,
On Fri, 4 Apr 2025 at 14:35, Marco Cavenati wrote:
> Almost. Unlike lseek(2), pread(2) and co. do not have side effects on the
> fd's offset.
> From the man page:
> > The pread() and pwrite() system calls are especially useful in
> > multithreaded applications. They allow multiple threads
On 04.04.25 09:46, Markus Armbruster wrote:
Vladimir Sementsov-Ogievskiy writes:
For now we only log the vhost device error, when virtqueue is actually
stopped. Let's add a QAPI event, which makes possible:
- collect statistics of such errors
- make immediate actions: take core dumps or d
On Thu, 3 Apr 2025 at 18:29, Fabiano Rosas wrote:
> Yes, there's no point. if we already have main and multifd channels,
> what's left must be postcopy.
* Okay.
> Well, but don't add it blindly if it doesn't make sense.
* Hmmn, okay. When I say/do things that seem reasonable to me, I'm
told - i
On 01.04.25 22:24, Eric Blake wrote:
On Tue, Mar 25, 2025 at 05:06:55PM +0100, Hanna Czenczek wrote:
We probably want to support larger write sizes than just 4k; 64k seems
nice. However, we cannot read partial requests from the FUSE FD, we
always have to read requests in full; so our read buffe
On 4/4/25 14:28, Daniel Henrique Barboza wrote:
Commit 5b4beba124 ("RISC-V Spike Machines") added the Spike machine and
made it default for qemu-system-riscv32/64. It was the first RISC-V
machine added in QEMU so setting it as default was sensible.
Today we have 7 riscv64 and 6 riscv32 machines
On 4/4/25 05:20, Pierrick Bouvier wrote:
Reported and fixed by Dmitry Kurakin.
Fixes: 54cb65d8588 ("plugin: add core code")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2901
Reviewed-by: Philippe Mathieu-Daudé
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2901
Signed-off-b
On 4/4/25 10:07 AM, Philippe Mathieu-Daudé wrote:
On 4/4/25 14:28, Daniel Henrique Barboza wrote:
Commit 5b4beba124 ("RISC-V Spike Machines") added the Spike machine and
made it default for qemu-system-riscv32/64. It was the first RISC-V
machine added in QEMU so setting it as default was sens
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Extract PSCI definitions (which are not target specific)
to the new "target/arm/psci.h", so code from hw/arm/ can
use them without having to include the target specific
"cpu.h" header.
Including cpu.h is not a problem to have common code (per arch
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Currently hvf_enabled() is restricted to target-specific code.
By defining CONFIG_HVF_IS_POSSIBLE we allow its use anywhere.
Instead, we can simply make hvf_enabled present for common and target
specific code, and link correct implementation, bas
On 3/19/25 15:27, Avihai Horon wrote:
On 18/03/2025 11:54, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
"hw/vfio/vfio-common.h" has been emptied of most of its declarations
by the previous changes and the only declarations left are related to
VFIODevice. Re
Enable accumulative mode for direct access mode operations. In direct access
mode, only a single source buffer is used, so the "iovec" count is set to 1.
If "acc_mode" is enabled:
1. Accumulate "total_req_len" with the current request length ("plen").
2. Check for padding and determine whether this
In the previous design, the I2C model would update I2CC_DMA_LEN (0x54) based on
the value of I2CM_DMA_LEN (0x1C) when the firmware set either I2CM_DMA_TX_ADDR
(0x30) or I2CM_DMA_RX_ADDR (0x34). However, this only worked correctly if the
firmware set I2CM_DMA_LEN before setting I2CM_DMA_TX_ADDR or I
On Wed, Mar 26, 2025 at 03:35:33PM +0100, Thomas Huth wrote:
> From: Thomas Huth
>
> This reverts commit e2668ba1ed44ad56f2f1653ff5f53b277d534fac.
>
> This commit made test 162 fail occasionally with:
>
> 162 fail [13:06:40] [13:06:40] 0.2s (last: 0.2s) output mismatch
> --- tests
On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
Hardware accelerators depends on the host, not the guest.
While this is true, no we can't unpoison those define.
They are applied per target, and not in config-host. So unpoisoining
them opens the possibility to miss something.
I would stick to
>-Original Message-
>From: Cédric Le Goater
>Subject: [PATCH for-10.1 12/32] vfio: Make vfio_group_list static
>
>vfio_group_list is only used in file "container.c".
>
>Signed-off-by: Cédric Le Goater
Reviewed-by: Zhenzhong Duan
Thanks
Zhenzhong
From: Thomas Huth
Since we don't run the Avocado jobs in the CI anymore, rename
these variables to QEMU_JOB_FUNCTIONAL and QEMU_CI_FUNCTIONAL_TESTING.
Also, there was a mismatch between the documentation and the
implementation of QEMU_CI_AVOCADO_TESTING: While the documentation
said that you had
Avoid direct use of address_space_memory.
Make use of the softmmu cache of the i/o page.
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/target/avr/helper.c b/target/avr/helper.c
index df7e2109d4..7cfd3d1093
On 3/20/25 15:29, Pierrick Bouvier wrote:
Those files will be compiled once per base architecture ("arm" in this
case), instead of being compiled for every variant/bitness of
architecture.
We make sure to not include target cpu definitions (exec/cpu-defs.h) by
defining header guard directly. Thi
On 4/4/2025 8:25 AM, Matheus Tavares Bernardino wrote:
On Thu, 3 Apr 2025 19:51:58 -0700 Brian Cain
wrote:
From: Brian Cain
Perhaps it would be best to reset the autorship here to
brian.c...@oss.qualcomm.com?
Good catch -- will do.
Signed-off-by: Brian Cain
---
target/hexagon/hex
On 4/4/25 15:00, Philippe Mathieu-Daudé wrote:
+qemu-block@
On 4/4/25 14:06, Cédric Le Goater wrote:
Hello,
On 4/2/25 11:14, Kane-Chen-AS wrote:
This patch introduces part of the Secure Boot Controller device,
which consists of several sub-components, including an OTP memory,
OTP controller,
On Fri, 21 Mar 2025 11:12:56 +0800
Bibo Mao wrote:
> In function virt_cpu_unplug(), it will send cpu unplug message to
> interrupt controller extioi and ipi irqchip. If there is problem in
> this function, system should continue to run and keep state the same
> before cpu is removed.
see my comm
On 01.04.25 15:44, Eric Blake wrote:
On Tue, Mar 25, 2025 at 05:06:35PM +0100, Hanna Czenczek wrote:
Polling in I/O functions can lead to nested read_from_fuse_export()
calls, overwriting the request buffer's content. The only function
affected by this is fuse_write(), which therefore must use
Vladimir Sementsov-Ogievskiy writes:
> On 04.04.25 09:20, Markus Armbruster wrote:
>> Vladimir Sementsov-Ogievskiy writes:
[...]
>>> +
>>> +``block-job-finalize`` (since 10.1)
>>> +''
>>> +
>>> +Use ``job-finalize`` instead.
>>> +
>>
>> block-job-finalize's doc
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