Hello,
On 4/2/25 11:14, Kane-Chen-AS wrote:
This patch introduces part of the Secure Boot Controller device,
which consists of several sub-components, including an OTP memory,
OTP controller, cryptographic engine, and boot controller.
In this version, the implementation includes the OTP memory and its
controller. The OTP memory can be programmed from within the guest
OS via a software utility.
What is the OTP memory ? An external flash device or built-in SRAM ?
If the latter, I suggest using an allocated buffer under the SBC model
and avoid the complexity of the BlockBackend implementation and
the definition of a drive on the command line for it. The
proposal is bypassing a lot of QEMU layers for this purpose.
Is the support the same for ast1030 and ast2600 SoC?
Thanks,
C.
Kane-Chen-AS (1):
hw/misc/aspeed_sbc: Implement OTP memory and controller
hw/misc/aspeed_sbc.c | 304 +++++++++++++++++++++++++++++++++++
include/hw/misc/aspeed_sbc.h | 14 ++
2 files changed, 318 insertions(+)
